DP83848KSQ/NOPB National Semiconductor, DP83848KSQ/NOPB Datasheet - Page 28

• Manufacturer Part Number: DP83848KSQ/NOPB
• Description: IC TXRX ETHERNET PHYTER 40-LLP
• Manufacturer: National Semiconductor
• Type: Transceiverr

Specifications of DP83848KSQ/NOPB

• Number Of Drivers/receivers: 1/1
• Protocol: Ethernet
• Voltage - Supply: 3 V ~ 3.6 V
• Mounting Type: Surface Mount
• Package / Case: 40-LLP
• For Use With: DP83848K-MAU-EK - BOARD EVALUATION DP83848K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: DP83848KSQ; DP83848KSQTR

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4.2.2.2 Base Line Wander Compensation
The DP83848K is completely ANSI TP-PMD compliant
and includes Base Line Wander (BLW) compensation.
The BLW compensation block can successfully recover
the TP-PMD defined “killer” pattern.
BLW can generally be defined as the change in the aver-
age DC content, relatively short period over time, of an AC
coupled digital transmission over a given transmission
medium. (i.e., copper wire).
BLW results from the interaction between the low fre-
quency components of a transmitted bit stream and the
frequency response of the AC coupling component(s)
within the transmission system. If the low frequency con-
tent of the digital bit stream goes below the low frequency
pole of the AC coupling transformers then the droop char-
acteristics of the transformers will dominate resulting in
potentially serious BLW.
The digital oscilloscope plot provided in Figure 9 illus-
trates the severity of the BLW event that can theoretically
be generated during 100BASE-TX packet transmission.
This event consists of approximately 800 mV of DC offset
for a period of 120 s. Left uncompensated, events such
as this can cause packet loss.
4.2.3 Signal Detect
The signal detect function of the DP83848K is incorpo-
rated to meet the specifications mandated by the ANSI
FDDI TP-PMD Standard as well as the IEEE 802.3
100BASE-TX Standard for both voltage thresholds and
timing parameters.
Note that the reception of normal 10BASE-T link pulses
and fast link pulses per IEEE 802.3u Auto-Negotiation by
the 100BASE-TX receiver do not cause the DP83848K to
assert signal detect.
Figure 9. 100BASE-TX BLW Event
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4.2.4 MLT-3 to NRZI Decoder
The DP83848K decodes the MLT-3 information from the
Digital Adaptive Equalizer block to binary NRZI data.
4.2.5 NRZI to NRZ
In a typical application, the NRZI to NRZ decoder is
required in order to present NRZ formatted data to the
descrambler.
4.2.6 Serial to Parallel
The 100BASE-TX receiver includes a Serial to Parallel
converter which supplies 5-bit wide data symbols to the
PCS Rx state machine.