PIC18F452-I/L Microchip Technology Inc., PIC18F452-I/L Datasheet - Page 24

• Manufacturer Part Number: PIC18F452-I/L
• Description: 44 PIN, 32 KB FLASH, 1536 RAM, 34 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F452-I/L

• A/d Inputs: 8-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 10 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 36
• Interface: I2C/SPI/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 44-pin PLCC
• Programmable Memory: 32K Bytes
• Ram Size: 1.5K Bytes
• Speed: 40 MHz
• Timers: 1-8-bit, 3-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC18FXX2
2.6.2
The PIC18FXX2 devices contain circuitry to prevent
“glitches” when switching between oscillator sources.
Essentially, the circuitry waits for eight rising edges of
the clock source that the processor is switching to. This
ensures that the new clock source is stable and that its
pulse width will not be less than the shortest pulse
width of the two clock sources.
FIGURE 2-8:
The sequence of events that takes place when switch-
ing from the Timer1 oscillator to the main oscillator will
depend on the mode of the main oscillator. In addition
to eight clock cycles of the main oscillator, additional
delays may take place.
FIGURE 2-9:
DS39564C-page 22
Program Counter
Note 1: T
Internal System
Note 1: Delay on internal system clock is eight oscillator cycles for synchronization.
(OSCCON<0>)
T1OSI
OSC1
Internal
System
Clock
SCS
(OSCCON<0>)
Program
Counter
T1OSI
OSC1
OSC2
Clock
SCS
OST
OSCILLATOR TRANSITIONS
Q1
= 1024 T
T
Q2
OSC
PC
Q3
Q3
PC
OSC
Q4
TIMING DIAGRAM FOR TRANSITION FROM OSC1 TO TIMER1 OSCILLATOR
TIMING FOR TRANSITION BETWEEN TIMER1 AND OSC1 (HS, XT, LP)
(drawing not to scale).
Q4
Q1
T
DLY
1
Q1
2
T
T
1
P
3
T
OST
4
Tscs
PC + 2
5
T
OSC
6
PC + 2
7
A timing diagram indicating the transition from the main
oscillator to the Timer1 oscillator is shown in
Figure 2-8. The Timer1 oscillator is assumed to be run-
ning all the time. After the SCS bit is set, the processor
is frozen at the next occurring Q1 cycle. After eight syn-
chronization cycles are counted from the Timer1 oscil-
lator, operation resumes. No additional delays are
required after the synchronization cycles.
If the main oscillator is configured for an external crys-
tal (HS, XT, LP), then the transition will take place after
an oscillator start-up time (T
diagram, indicating the transition from the Timer1 oscil-
lator to the main oscillator for HS, XT and LP modes, is
shown in Figure 2-9.
1
8
2
Q1
3
Q2
4
T
T
T
SCS
1
Q3
P
5
6
Q4
© 2006 Microchip Technology Inc.
7
OST
Q1
Q1
8
) has occurred. A timing
Q2 Q3
Q2
PC + 4
Q3
Q4
Q1 Q2
Q4
PC + 6
Q1
Q3