PIC18F452-I/L Microchip Technology Inc., PIC18F452-I/L Datasheet - Page 95

• Manufacturer Part Number: PIC18F452-I/L
• Description: 44 PIN, 32 KB FLASH, 1536 RAM, 34 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F452-I/L

• A/d Inputs: 8-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 10 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 36
• Interface: I2C/SPI/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 44-pin PLCC
• Programmable Memory: 32K Bytes
• Ram Size: 1.5K Bytes
• Speed: 40 MHz
• Timers: 1-8-bit, 3-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

9.3
PORTC is an 8-bit wide, bi-directional port. The corre-
sponding Data Direction register is TRISC. Setting a
TRISC bit (= 1) will make the corresponding PORTC
pin an input (i.e., put the corresponding output driver in
a Hi-Impedance mode). Clearing a TRISC bit (= 0) will
make the corresponding PORTC pin an output (i.e., put
the contents of the output latch on the selected pin).
The Data Latch register (LATC) is also memory
mapped. Read-modify-write operations on the LATC
register reads and writes the latched output value for
PORTC.
PORTC is multiplexed with several peripheral functions
(Table 9-5). PORTC pins have Schmitt Trigger input
buffers.
When enabling peripheral functions, care should be
taken in defining TRIS bits for each PORTC pin. Some
peripherals override the TRIS bit to make a pin an out-
put, while other peripherals override the TRIS bit to
make a pin an input. The user should refer to the corre-
sponding peripheral section for the correct TRIS bit
settings.
FIGURE 9-7:
© 2006 Microchip Technology Inc.
Note:
Note 1:
PORTC, TRISC and LATC
Registers
On a Power-on Reset, these pins are
configured as digital inputs.
2:
3:
I/O pins have diode protection to V
Port/Peripheral Select signal selects between port data (input) and peripheral output.
Peripheral Output Enable is only active if peripheral select is active.
PORTC BLOCK DIAGRAM (PERIPHERAL OUTPUT OVERRIDE)
RD LATC
RD TRISC
Peripheral Output
RD PORTC
Peripheral Data Out
WR LATC or
WR PORTC
WR TRISC
Enable
Port/Peripheral Select
Data Bus
Peripheral Data In
(3)
DD
and V
(2)
TRIS Latch
Data Latch
CK
CK
D
D
SS
.
Q
Q
Q
Q
The pin override value is not loaded into the TRIS reg-
ister. This allows read-modify-write of the TRIS register,
without concern due to peripheral overrides.
RC1 is normally configured by configuration bit,
CCP2MX, as the default peripheral pin of the CCP2
module (default/erased state, CCP2MX = ’1’).
EXAMPLE 9-3:
0
1
CLRF
CLRF
MOVLW 0xCF
MOVWF TRISC
Q
EN
D
PORTC
LATC
V
V
P
N
DD
SS
; Initialize PORTC by
; clearing output
; data latches
; Alternate method
; to clear output
; data latches
; Value used to
; initialize data
; direction
; Set RC<3:0> as inputs
; RC<5:4> as outputs
; RC<7:6> as inputs
INITIALIZING PORTC
PIC18FXX2
I/O pin
Schmitt
Trigger
(1)
DS39564C-page 93