PIC18F2520-I/SP Microchip Technology Inc., PIC18F2520-I/SP Datasheet - Page 310
![no-image](/images/manufacturer_photos/0/4/440/microchip_technology_inc__sml.jpg)
PIC18F2520-I/SP
Manufacturer Part Number
PIC18F2520-I/SP
Description
28 Pin, 32 KB Flash, 1536 RAM, 25 I/O
Manufacturer
Microchip Technology Inc.
Datasheet
1.PIC18F2520-ISP.pdf
(390 pages)
Specifications of PIC18F2520-I/SP
A/d Inputs
10-Channel, 10-Bit
Comparators
2
Cpu Speed
10 MIPS
Eeprom Memory
256 Bytes
Input Output
25
Interface
I2C/SPI/USART
Memory Type
Flash
Number Of Bits
8
Package Type
28-pin SPDIP
Programmable Memory
32K Bytes
Ram Size
1.5K Bytes
Speed
40 MHz
Timers
1-8-bit, 3-16-bit
Voltage, Range
2-5.5 V
Lead Free Status / Rohs Status
RoHS Compliant part
Electrostatic Device
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F2520-I/SP
Manufacturer:
XLSEMI
Quantity:
35 000
Part Number:
PIC18F2520-I/SP
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
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PIC18F2420/2520/4420/4520
XORWF
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
DS39631A-page 308
Q Cycle Activity:
Before Instruction
After Instruction
Decode
REG
W
REG
W
Q1
=
=
=
=
register ‘f’
Exclusive OR W with f
XORWF
0
d
a
(W) .XOR. (f)
N, Z
Exclusive OR the contents of W with
register ‘f’. If ‘d’ is ‘0’, the result is stored
in W. If ‘d’ is ‘1’, the result is stored back
in the register ‘f’ (default).
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f
Section 24.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
1
1
XORWF
Read
0001
Q2
f
AFh
B5h
1Ah
B5h
[0,1]
[0,1]
255
REG, 1, 0
f {,d {,a}}
10da
Process
Data
dest
Q3
95 (5Fh). See
ffff
destination
Write to
Q4
ffff
Preliminary
2004 Microchip Technology Inc.
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