PIC12F629-I/SN Microchip Technology Inc., PIC12F629-I/SN Datasheet - Page 29

• Manufacturer Part Number: PIC12F629-I/SN
• Description: 8 PIN, 1.75 KB FLASH, 64 RAM, 6 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC12F629-I/SN

• Comparators: 1
• Cpu Speed: 5 MIPS
• Eeprom Memory: 128 Bytes
• Input Output: 5
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 8-pin SOIC-N
• Programmable Memory: 1.75K Bytes
• Ram Size: 64 Bytes
• Speed: 20 MHz
• Timers: 1-8-bit, 1-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

4.0
The Timer0 module timer/counter has the following
features:
• 8-bit timer/counter
• Readable and writable
• 8-bit software programmable prescaler
• Internal or external clock select
• Interrupt on overflow from FFh to 00h
• Edge select for external clock
Figure 4-1 is a block diagram of the Timer0 module and
the prescaler shared with the WDT.
4.1
Timer mode is selected by clearing the T0CS bit
(OPTION_REG<5>). In Timer mode, the Timer0
module will increment every instruction cycle (without
prescaler). If TMR0 is written, the increment is inhibited
for the following two instruction cycles. The user can
work around this by writing an adjusted value to the
TMR0 register.
FIGURE 4-1:
 2003 Microchip Technology Inc.
T0CKI
Note:
pin
(= F
CLKOUT
Note 1: T0SE, T0CS, PSA, PS0-PS2 are bits in the Option register.
OSC
T0SE
TIMER0 MODULE
Timer0 Operation
Additional information on the Timer0
module is available in the PICmicro
Range Reference Manual, (DS33023).
/4)
Watchdog
WDTE
Timer
BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER
T0CS
0
1
PSA
0
1
TM
Prescaler
Mid-
8-bit
8
PS0 - PS2
Counter mode is selected by setting the T0CS bit
(OPTION_REG<5>). In this mode, the Timer0 module
will increment either on every rising or falling edge of
pin GP2/T0CKI. The incrementing edge is determined
by
(OPTION_REG<4>). Clearing the T0SE bit selects the
rising edge.
4.2
A Timer0 interrupt is generated when the TMR0
register timer/counter overflows from FFh to 00h. This
overflow sets the T0IF bit. The interrupt can be masked
by
(INTCON<2>) must be cleared in software by the
Timer0 module Interrupt Service Routine before re-
enabling this interrupt. The Timer0 interrupt cannot
wake the processor from SLEEP since the timer is
shut-off during SLEEP.
Note:
clearing the T0IE bit (INTCON<5>). The T0IF bit
the
Timer0 Interrupt
Counter mode has specific external clock
requirements. Additional information on
these requirements is available in the
PICmicro
Manual, (DS33023).
PSA
PSA
source
1
0
1
0
PIC12F629/675
SYNC 2
TM
Cycles
Time-out
edge
WDT
Mid-Range
(T0SE)
Data Bus
Set Flag bit T0IF
8
DS41190C-page 27
TMR0
on Overflow
control
Reference
bit