PIC12F629-I/SN Microchip Technology Inc., PIC12F629-I/SN Datasheet - Page 51

• Manufacturer Part Number: PIC12F629-I/SN
• Description: 8 PIN, 1.75 KB FLASH, 64 RAM, 6 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC12F629-I/SN

• Comparators: 1
• Cpu Speed: 5 MIPS
• Eeprom Memory: 128 Bytes
• Input Output: 5
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 8-pin SOIC-N
• Programmable Memory: 1.75K Bytes
• Ram Size: 64 Bytes
• Speed: 20 MHz
• Timers: 1-8-bit, 1-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

8.3
To read a data memory location, the user must write
the address to the EEADR register and then set con-
trol bit RD (EECON1<0>), as shown in Example 8-1.
The data is available, in the very next cycle, in the
EEDATA register. Therefore, it can be read in the next
instruction. EEDATA holds this value until another
read, or until it is written to by the user (during a write
operation).
EXAMPLE 8-1:
8.4
To write an EEPROM data location, the user must first
write the address to the EEADR register and the data
to the EEDATA register. Then the user must follow a
specific sequence to initiate the write for each byte, as
shown in Example 8-2.
EXAMPLE 8-2:
The write will not initiate if the above sequence is not
exactly followed (write 55h to EECON2, write AAh to
EECON2, then set WR bit) for each byte. We strongly
recommend that interrupts be disabled during this
code segment. A cycle count is executed during the
required sequence. Any number that is not equal to the
required cycles to execute the required sequence will
prevent the data from being written into the EEPROM.
Additionally, the WREN bit in EECON1 must be set to
enable write. This mechanism prevents accidental
writes to data EEPROM due to errant (unexpected)
code execution (i.e., lost programs). The user should
keep the WREN bit clear at all times, except when
updating EEPROM. The WREN bit is not cleared
by hardware.
 2003 Microchip Technology Inc.
bsf
movlw CONFIG_ADDR
movwf EEADR
bsf
movf
bsf
bsf
bcf
movlw 55h
movwf EECON2
movlw AAh
movwf EECON2
bsf
bsf
READING THE EEPROM DATA
MEMORY
WRITING TO THE EEPROM DATA
MEMORY
STATUS,RP0
EECON1,RD
EEDATA,W
STATUS,RP0
EECON1,WREN
INTCON,GIE
EECON1,WR
INTCON,GIE
DATA EEPROM READ
DATA EEPROM WRITE
;Bank 1
;
;Address to read
;EE Read
;Move data to W
;Bank 1
;Enable write
;Disable INTs
;Unlock write
;
;
;
;Start the write
;Enable INTS
After a write sequence has been initiated, clearing the
WREN bit will not affect this write cycle. The WR bit will
be inhibited from being set unless the WREN bit is set.
At the completion of the write cycle, the WR bit is
cleared in hardware and the EE Write Complete
Interrupt Flag bit (EEIF) is set. The user can either
enable this interrupt or poll this bit. The EEIF bit
(PIR<7>) register must be cleared by software.
8.5
Depending on the application, good programming
practice may dictate that the value written to the Data
EEPROM should be verified (see Example 8-3) to the
desired value to be written.
EXAMPLE 8-3:
8.5.1
The Data EEPROM is a high-endurance, byte addres-
sable array that has been optimized for the storage of
frequently
variables or other data that are updated often).
Frequently changing values will typically be updated
more often than specifications D120 or D120A. If this is
not the case, an array refresh must be performed. For
this reason, variables that change infrequently (such as
constants, IDs, calibration, etc.) should be stored in
FLASH program memory.
8.6
There are conditions when the device may not want to
write to the data EEPROM memory. To protect against
spurious EEPROM writes, various mechanisms have
been built in. On power-up, WREN is cleared. Also, the
Power-up
EEPROM write.
The write initiate sequence and the WREN bit together
help prevent an accidental write during:
• brown-out
• power glitch
• software malfunction
bcf
:
bsf
movf
bsf
xorwf EEDATA,W
btfss STATUS,Z
goto
:
WRITE VERIFY
PROTECTION AGAINST
SPURIOUS WRITE
USING THE DATA EEPROM
changing
Timer
STATUS,RP0
STATUS,RP0
EEDATA,W
EECON1,RD
WRITE_ERR
PIC12F629/675
(72
WRITE VERIFY
information
ms
;Bank 0
;Any code
;Bank 1 READ
;EEDATA not changed
;from previous write
;YES, Read the
;value written
;Is data the same
;No, handle error
;Yes, continue
duration)
DS41190C-page 49
(e.g.,
prevents
program