PIC18F6520-I/PT Microchip Technology Inc., PIC18F6520-I/PT Datasheet - Page 164

• Manufacturer Part Number: PIC18F6520-I/PT
• Description: 64 PIN, 32 KB FLASH, 2048 RAM, 52 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F6520-I/PT

• A/d Inputs: 12-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 10 MIPS
• Eeprom Memory: 1024 Bytes
• Input Output: 52
• Interface: I2C/SPI/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 64-pin TQFP
• Programmable Memory: 32K Bytes
• Ram Size: 2K Bytes
• Speed: 40 MHz
• Timers: 2-8 bit, 3-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC18F6520/8520/6620/8620/6720/8720
17.3.5
The master can initiate the data transfer at any time
because it controls the SCK. The master determines
when the slave (Processor 2, Figure 17-2) is to
broadcast data by the software protocol.
In Master mode, the data is transmitted/received as
soon as the SSPBUF register is written to. If the SPI is
only going to receive, the SDO output could be dis-
abled (programmed as an input). The SSPSR register
will continue to shift in the signal present on the SDI pin
at the programmed clock rate. As each byte is
received, it will be loaded into the SSPBUF register as
if a normal received byte (interrupts and status bits
appropriately set). This could be useful in receiver
applications as a “Line Activity Monitor” mode.
The clock polarity is selected by appropriately program-
ming the CKP bit (SSPCON1<4>). This then, would
give waveforms for SPI communication, as shown in
FIGURE 17-3:
DS39609B-page 162
Write to
SSPBUF
SCK
(CKP = 0
CKE = 0)
SCK
(CKP = 1
CKE = 0)
SCK
(CKP = 0
CKE = 1)
SCK
(CKP = 1
CKE = 1)
SDO
(CKE = 0)
SDO
(CKE = 1)
SDI
(SMP = 0)
Input
Sample
(SMP = 0)
SDI
(SMP = 1)
Input
Sample
(SMP = 1)
SSPIF
SSPSR to
SSPBUF
MASTER MODE
SPI MODE WAVEFORM (MASTER MODE)
bit 7
bit 7
bit 7
bit 7
bit 6
bit 6
bit 5
bit 5
bit 4
bit 4
Figure 17-3, Figure 17-5 and Figure 17-6, where the
MSB is transmitted first. In Master mode, the SPI clock
rate (bit rate) is user-programmable to be one of the
following:
• F
• F
• F
• Timer2 output/2
This allows a maximum data rate (at 40 MHz) of
10.00 Mbps.
Figure 17-3 shows the waveforms for Master mode.
When the CKE bit is set, the SDO data is valid before
there is a clock edge on SCK. The change of the input
sample is shown based on the state of the SMP bit. The
time when the SSPBUF is loaded with the received
data is shown.
bit 3
bit 3
OSC
OSC
OSC
/4 (or T
/16 (or 4 • T
/64 (or 16 • T
bit 2
bit 2
CY
)
CY
bit 1
bit 1
CY
)
)
 2004 Microchip Technology Inc.
bit 0
bit 0
bit 0
bit 0
Next Q4 cycle
after Q2
4 Clock
Modes