PIC18LF4520-I/PT Microchip Technology Inc., PIC18LF4520-I/PT Datasheet - Page 56
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PIC18LF4520-I/PT
Manufacturer Part Number
PIC18LF4520-I/PT
Description
44 Pin, 32 KB Flash, 1536 RAM, 36 I/O
Manufacturer
Microchip Technology Inc.
Datasheet
1.PIC18LF4520-IPT.pdf
(390 pages)
Specifications of PIC18LF4520-I/PT
A/d Inputs
13-Channel, 10-Bit
Comparators
2
Cpu Speed
10 MIPS
Eeprom Memory
256 Bytes
Input Output
36
Interface
I2C/SPI/UART/USART
Memory Type
Flash
Number Of Bits
8
Package Type
44-pin TQFP
Programmable Memory
32K Bytes
Ram Size
1.5K Bytes
Speed
40 MHz
Timers
1-8-bit, 3-16-bit
Voltage, Range
2-5.5 V
Lead Free Status / Rohs Status
RoHS Compliant part
Electrostatic Device
Available stocks
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Quantity
Price
Company:
Part Number:
PIC18LF4520-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
Part Number:
PIC18LF4520-I/PT
Manufacturer:
MICROCHI
Quantity:
20 000
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PIC18F2420/2520/4420/4520
5.1.1
The Program Counter (PC) specifies the address of the
instruction to fetch for execution. The PC is 21 bits wide
and is contained in three separate 8-bit registers. The
low byte, known as the PCL register, is both readable
and writable. The high byte, or PCH register, contains
the PC<15:8> bits; it is not directly readable or writable.
Updates to the PCH register are performed through the
PCLATH register. The upper byte is called PCU. This
register contains the PC<20:16> bits; it is also not
directly readable or writable. Updates to the PCU
register are performed through the PCLATU register.
The contents of PCLATH and PCLATU are transferred
to the program counter by any operation that writes
PCL. Similarly, the upper two bytes of the program
counter are transferred to PCLATH and PCLATU by an
operation that reads PCL. This is useful for computed
offsets to the PC (see Section 5.1.4.1 “Computed
GOTO”).
The PC addresses bytes in the program memory. To
prevent the PC from becoming misaligned with word
instructions, the Least Significant bit of PCL is fixed to
a value of ‘0’. The PC increments by 2 to address
sequential instructions in the program memory.
The CALL, RCALL, GOTO and program branch
instructions write to the program counter directly. For
these instructions, the contents of PCLATH and
PCLATU are not transferred to the program counter.
5.1.2
The return address stack allows any combination of up
to 31 program calls and interrupts to occur. The PC is
pushed onto the stack when a CALL or RCALL instruc-
tion is executed or an interrupt is Acknowledged. The
PC value is pulled off the stack on a RETURN, RETLW
or a RETFIE instruction. PCLATU and PCLATH are not
affected by any of the RETURN or CALL instructions.
FIGURE 5-2:
DS39631A-page 54
PROGRAM COUNTER
RETURN ADDRESS STACK
TOSU
00h
Top-of-Stack Registers
RETURN ADDRESS STACK AND ASSOCIATED REGISTERS
TOSH
1Ah
TOSL
34h
Top-of-Stack
Return Address Stack <20:0>
Preliminary
001A34h
000D58h
readable and writable. A set of three registers,
The stack operates as a 31-word by 21-bit RAM and a
5-bit stack pointer, STKPTR. The stack space is not
part of either program or data space. The stack pointer
is readable and writable and the address on the top of
the stack is readable and writable through the top-of-
stack Special File Registers. Data can also be pushed
to, or popped from the stack, using these registers.
A CALL type instruction causes a push onto the stack;
the stack pointer is first incremented and the location
pointed to by the stack pointer is written with the
contents of the PC (already pointing to the instruction
following the CALL). A RETURN type instruction causes
a pop from the stack; the contents of the location
pointed to by the STKPTR are transferred to the PC
and then the stack pointer is decremented.
The stack pointer is initialized to ‘00000’ after all
Resets. There is no RAM associated with the location
corresponding to a stack pointer value of ‘00000’; this
is only a Reset value. Status bits indicate if the stack is
full or has overflowed or has underflowed.
5.1.2.1
Only the top of the return address stack (TOS) is
TOSU:TOSH:TOSL, hold the contents of the stack loca-
tion pointed to by the STKPTR register (Figure 5-2). This
allows users to implement a software stack if necessary.
After a CALL, RCALL or interrupt, the software can read
the pushed value by reading the TOSU:TOSH:TOSL
registers. These values can be placed on a user defined
software stack. At return time, the software can return
these values to TOSU:TOSH:TOSL and do a return.
The user must disable the global interrupt enable bits
while accessing the stack to prevent inadvertent stack
corruption.
11111
11110
11101
00011
00010
00001
00000
Top-of-Stack Access
2004 Microchip Technology Inc.
Stack Pointer
STKPTR<4:0>
00010
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