DSPIC33FJ256MC710-I/PF Microchip Technology Inc., DSPIC33FJ256MC710-I/PF Datasheet - Page 283
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DSPIC33FJ256MC710-I/PF
Manufacturer Part Number
DSPIC33FJ256MC710-I/PF
Description
16 BIT MCU/DSP 100LD 40MIPS 256KB FLASH
Manufacturer
Microchip Technology Inc.
Type
DSPr
Datasheet
1.DSPIC33FJ256MC710-IPF.pdf
(371 pages)
Specifications of DSPIC33FJ256MC710-I/PF
A/d Inputs
24-Channels, 12-Bit
Comparators
8
Cpu Speed
40 MIPS
Eeprom Memory
0 Bytes
Input Output
85
Interface
I2C/SPI/UART
Ios
85
Memory Type
Flash
Number Of Bits
16
Package Type
100-pin TQFP
Programmable Memory
256K Bytes
Ram Size
30K Bytes
Timers
9-16-bit, 4-32-bit
Voltage, Range
3-3.6
Lead Free Status / Rohs Status
RoHS Compliant part
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REGISTER 22-2:
© 2006 Microchip Technology Inc.
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15-13
bit 12-11
bit 10
bit 9-8
bit 7
bit 6
bit 5-2
bit 1
R/W-0
BUFS
R-0
VCFG<2:0>: Converter Voltage Reference Configuration bits
Unimplemented: Read as ‘0’
CSCNA: Scan Input Selections for CH0+ during Sample A bit
1 = Scan inputs
0 = Do not scan inputs
CHPS<1:0>: Selects Channels Utilized bits
When AD12B = 1, CHPS<1:0> is: U-0, Unimplemented, Read as ‘0’
1x = Converts CH0, CH1, CH2 and CH3
01 = Converts CH0 and CH1
00 = Converts CH0
BUFS: Buffer Fill Status bit (only valid when BUFM = 1)
1 = ADC is currently filling buffer 0x8-0xF, user should access data in 0x0-0x7
0 = ADC is currently filling buffer 0x0-0x7, user should access data in 0x8-0xF
Unimplemented: Read as ‘0’
SMPI<3:0>: Selects Increment Rate for DMA Addresses bits or number of sample/conversion
operations per interrupt.
1111 = Increments the DMA address or generates interrupt after completion of every 16th
1110 = Increments the DMA address or generates interrupt after completion of every 15th
• • •
0001 = Increments the DMA address or generates interrupt after completion of every 2nd
0000 = Increments the DMA address or generates interrupt after completion of every
BUFM: Buffer Fill Mode Select bit
1 = Starts buffer filling at address 0x0 on first interrupt and 0x8 on next interrupt
0 = Always starts filling buffer at address 0x0
VCFG<2:0>
000
001
010
011
1xx
R/W-0
U-0
—
ADxCON2: ADCx CONTROL REGISTER 2 (where x = 1 or 2)
sample/conversion operation
sample/conversion operation
sample/conversion operation
sample/conversion operation
External V
External V
ADREF+
A
A
A
W = Writable bit
‘1’ = Bit is set
VDD
VDD
VDD
R/W-0
R/W-0
REF
REF
+
+
External V
External V
ADREF-
R/W-0
A
A
Avss
Preliminary
U-0
VSS
VSS
—
SMPI<3:0>
REF
REF
-
-
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
R/W-0
U-0
—
CSCNA
R/W-0
R/W-0
x = Bit is unknown
dsPIC33F
R/W-0
R/W-0
BUFM
CHPS<1:0>
DS70165D-page 281
R/W-0
R/W-0
ALTS
bit 8
bit 0
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