DSPIC30F2023-30I/PT Microchip Technology Inc., DSPIC30F2023-30I/PT Datasheet - Page 280
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DSPIC30F2023-30I/PT
Manufacturer Part Number
DSPIC30F2023-30I/PT
Description
DSP, 16-Bit, 12KB Flash, 512 RAM, 35 I/O, TQFP-44
Manufacturer
Microchip Technology Inc.
Type
DSPr
Datasheet
1.DSPIC30F2023-30IPT.pdf
(286 pages)
Specifications of DSPIC30F2023-30I/PT
A/d Inputs
12-Channels, 10-Bit
Comparators
4
Cpu Speed
30 MIPS
Eeprom Memory
0 Bytes
Input Output
35
Interface
I2C/SPI/UART
Ios
35
Memory Type
Flash
Number Of Bits
16
Package Type
44-pin TQFP
Programmable Memory
12K Bytes
Ram Size
512 Bytes
Timers
3-16-bit, 1-32-bit
Voltage, Range
3-5.5
Lead Free Status / Rohs Status
RoHS Compliant part
Electrostatic Device
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dsPIC30F1010/202X
E
Electrical Characteristics................................................... 231
Equations
Errata .................................................................................... 8
External Clock Input .......................................................... 207
External Clock Timing Characteristics
External Clock Timing Requirements................................ 241
External Interrupt Requests ................................................ 51
F
Fast Context Saving............................................................ 51
Firmware Instructions........................................................ 219
Flash Program Memory....................................................... 81
I
I/O Pin Specifications
I/O Ports .............................................................................. 77
I
I
I
I
I
DS70178C-page 278
2
2
2
2
2
C ..................................................................................... 153
C 10-bit Slave Mode Operation ...................................... 155
C 7-bit Slave Mode Operation ........................................ 155
C Master Mode
C Module
AC ............................................................................. 240
I
Relationship Between Device and SPI
UART Baud Rate with BRGH = 0 ............................. 162
UART Baud Rate with BRGH = 1 ............................. 162
Type A, B and C Timer ............................................. 249
Type A Timer ............................................................ 249
Type B Timer ............................................................ 250
Type C Timer ............................................................ 250
In-Circuit Serial Programming (ICSP) ......................... 81
Run-Time Self-Programming (RTSP) ......................... 81
Table Instruction Operation Summary ........................ 81
Input .......................................................................... 239
Output ....................................................................... 239
Parallel I/O (PIO)......................................................... 77
Reception .................................................................. 155
Transmission............................................................. 155
Reception .................................................................. 155
Transmission............................................................. 155
Baud Rate Generator ................................................ 158
Clock Arbitration........................................................ 158
Multi-Master Communication, Bus Collision
Reception .................................................................. 157
Transmission............................................................. 157
Addresses ................................................................. 155
Bus Data Timing Characteristics
Bus Data Timing Requirements
Bus Start/Stop Bits Timing Characteristics
General Call Address Support .................................. 157
Interrupts ................................................................... 156
IPMI Support ............................................................. 157
Master Operation ...................................................... 157
Master Support ......................................................... 157
Operating Function Description ................................ 153
Operation During CPU Sleep and Idle Modes .......... 158
2
C ............................................................................. 158
Clock Speed...................................................... 148
and Bus Arbitration ........................................... 158
Master Mode ..................................................... 259
Slave Mode ....................................................... 261
Master Mode ..................................................... 260
Slave Mode ....................................................... 262
Master Mode ..................................................... 259
Slave Mode ....................................................... 261
Preliminary
I
Idle Current (I
In-Circuit Debugger........................................................... 217
In-Circuit Serial Programming (ICSP)............................... 197
Initialization Condition for RCON Register Case 1 ........... 213
Initialization Condition for RCON Register Case 2 ........... 213
Input Capture (CAPX) Timing Characteristics .................. 251
Input Capture Interrupts...................................................... 99
Input Capture Module ......................................................... 97
Input Capture Register Map.............................................. 100
Input Capture Timing Requirements................................. 251
Input Change Notification ................................................... 78
Input Change Notification Register Map ............................. 80
Instruction Addressing Modes ............................................ 41
Instruction Set................................................................... 219
Instruction Set Overview................................................... 222
Inter-Integrated Circuit. See I
Internal Clock Timing Examples ....................................... 242
Internet Address ............................................................... 273
Interrupt Control and Status Register (INTTREG) .............. 74
Interrupt Control Register 1 (INTCON1) ............................. 52
Interrupt Control Register 2 (INTCON2) ............................. 54
Interrupt Controller Register Map ....................................... 75
Interrupt Enable Control Register 1 (IEC1)......................... 61
Interrupt Enable Control Register 2 (IEC2)......................... 62
Interrupt Flag Status Register 0 (IFS0)............................... 55
Interrupt Flag Status Register 1 (IFS1)............................... 57
Interrupt Flag Status Register 2 (IFS2)............................... 58
Interrupt Priority .................................................................. 48
Interrupt Priority Control Register 0 (IPC0)......................... 63
Interrupt Priority Control Register 1 (IPC1)......................... 64
Interrupt Priority Control Register 10 (IPC10)..................... 73
Interrupt Priority Control Register 2 (IPC2)......................... 65
Interrupt Priority Control Register 3 (IPC3)......................... 66
Interrupt Priority Control Register 4 (IPC4)......................... 67
Interrupt Priority Control Register 5 (IPC5)......................... 68
Interrupt Priority Control Register 6 (IPC6)......................... 69
Interrupt Priority Control Register 7 (IPC7)......................... 70
Interrupt Priority Control Register 8 (IPC8)......................... 71
Interrupt Priority Control Register 9 (IPC9)......................... 72
Interrupt Sequence ............................................................. 51
Interrupts............................................................................. 47
L
Leading Edge Blanking Control Register (LEBCONx)...... 120
Linear Feedback Register (LFSR) .................................... 202
Load Conditions................................................................ 240
2
C Register Map .............................................................. 159
Pin Configuration ...................................................... 153
Programmer’s Model ................................................ 153
Registers .................................................................. 153
Slope Control ............................................................ 157
Software Controlled Clock Stretching (STREN = 1) . 156
Various Modes.......................................................... 153
Simple Capture Event Mode....................................... 98
Sleep and Idle Modes ................................................. 99
File Register Instructions ............................................ 41
Fundamental Modes Supported ................................. 41
MAC Instructions ........................................................ 42
MCU Instructions ........................................................ 42
Move and Accumulator Instructions............................ 42
Other Instructions ....................................................... 42
Interrupt Stack Frame ................................................. 51
Traps .......................................................................... 49
IDLE
) ............................................................ 235
© 2006 Microchip Technology Inc.
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