PIC18F45K22-I/P Microchip Technology Inc., PIC18F45K22-I/P Datasheet - Page 355

• Manufacturer Part Number: PIC18F45K22-I/P
• Description: 40 PDIP .600in TUBE, 32KB, Flash, 1536bytes-RAM, 8-bit Family, nanoWatt XLP
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F45K22-I/P

• A/d Inputs: 28-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 16 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 35
• Interface: I2C/SPI/UART/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 40-pin PDIP
• Programmable Memory: 32K Bytes
• Ram Size: 1.5K Bytes
• Speed: 64 MHz
• Temperature Range: –40 to 125 °C
• Timers: 3-8-bit, 4-16-bit
• Voltage, Range: 1.8-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

REGISTER 24-5:
REGISTER 24-6:
 2010 Microchip Technology Inc.
bit 7
Legend:
R = Readable bit
-n = Value when device is unprogrammed
bit 7
bit 6
bit 5-3
bit 2
bit 1
bit 0
Note 1:
bit 7
Legend:
R = Readable bit
-n = Value when device is unprogrammed
bit 7-4
bit 3
bit 2
bit 1
bit 0
Note 1:
DEBUG
R/P-1
U-0
—
2:
(2)
Can only be changed by a programmer in high-voltage programming mode.
The DEBUG bit is managed automatically by device development tools including debuggers and programmers. For
normal device operations, this bit should be maintained as a ‘1’.
Available on PIC18(L)FX5K22 and PIC18(L)FX6K22 devices.
DEBUG: Background Debugger Enable bit
1 = Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins
0 = Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug
XINST: Extended Instruction Set Enable bit
1 = Instruction set extension and Indexed Addressing mode enabled
0 = Instruction set extension and Indexed Addressing mode disabled (Legacy mode)
Unimplemented: Read as ‘0’
LVP: Single-Supply ICSP Enable bit
1 = Single-Supply ICSP enabled
0 = Single-Supply ICSP disabled
Unimplemented: Read as ‘0’
STVREN: Stack Full/Underflow Reset Enable bit
1 = Stack full/underflow will cause Reset
0 = Stack full/underflow will not cause Reset
Unimplemented: Read as ‘0’
CP3: Code Protection bit
1 = Block 3 not code-protected
0 = Block 3 code-protected
CP2: Code Protection bit
1 = Block 2 not code-protected
0 = Block 2 code-protected
CP1: Code Protection bit
1 = Block 1 not code-protected
0 = Block 1 code-protected
CP0: Code Protection bit
1 = Block 0 not code-protected
0 = Block 0 code-protected
XINST
R/P-0
U-0
—
CONFIG4L: CONFIGURATION REGISTER 4 LOW
CONFIG5L: CONFIGURATION REGISTER 5 LOW
P = Programmable bit
U-0
U-0
—
—
(1)
(1)
U-0
U-0
Preliminary
—
—
(2)
U = Unimplemented bit, read as ‘0’
x = Bit is unknown
U = Unimplemented bit, read as ‘0’
C = Clearable only bit
CP3
R/C-1
U-0
—
PIC18(L)F2X/4XK22
(1)
CP2
R/C-1
LVP
R/P-1
(1)
(1)
R/C-1
CP1
U-0
—
DS41412D-page 355
STVREN
R/P-1
R/C-1
CP0
bit 0
bit 0