PIC24FJ64GA006-I/PT Microchip Technology Inc., PIC24FJ64GA006-I/PT Datasheet - Page 131

• Manufacturer Part Number: PIC24FJ64GA006-I/PT
• Description: 64 PIN, 64KB FLASH, 8 KB RAM, 53 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC24FJ64GA006-I/PT

• A/d Inputs: 16 Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 16 MIPS
• Eeprom Memory: 0 Bytes
• Input Output: 53
• Interface: I2C/SPI/UART
• Memory Capacity: 64 Kbytes
• Memory Type: Flash
• Number Of Bits: 16
• Number Of Inputs: 53
• Number Of Pins: 64
• Package Type: 64-pin TQFP
• Programmable Memory: 64K Bytes
• Ram Size: 8K Bytes
• Speed: 16 MHz
• Timers: 5-16-bit
• Voltage, Range: 2-3.6 V
• Voltage, Rating: 2-3.6 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

REGISTER 15-2:
© 2006 Microchip Technology Inc.
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
.
Upper Byte:
bit 15
ACKSTAT
R-0 HSC
D/A: Data/Address bit (when operating as I
1 = Indicates that the last byte received was data
0 = Indicates that the last byte received was device address
Hardware clear at device address match.
Hardware set by write to I2CxTRN or by reception of slave byte.
P: Stop bit
1 = Indicates that a Stop bit has been detected last
0 = Stop bit was not detected last
Hardware set or clear when Start, Repeated Start or Stop detected.
S: Start bit
1 = Indicates that a Start (or Repeated Start) bit has been detected last
0 = Start bit was not detected last
Hardware set or clear when Start, Repeated Start or Stop detected.
R/W: Read/Write bit Information (when operating as I
1 = Read – indicates data transfer is output from slave
0 = Write – indicates data transfer is input to slave
Hardware set or clear after reception of I
RBF: Receive Buffer Full Status bit
1 = Receive complete, I2CxRCV is full
0 = Receive not complete, I2CxRCV is empty
Hardware set when I2CxRCV written with received byte.
Hardware clear when software reads I2CxRCV.
TBF: Transmit Buffer Full Status bit
1 = Transmit in progress, I2CxTRN is full
0 = Transmit complete, I2CxTRN is empty
Hardware set when software writes I2CxTRN.
Hardware clear at completion of data transmission.
Legend:
R = Readable bit
-n = Value at POR
R-0 HSC
TRSTAT
Lower Byte:
bit 7
R/C-0 HS
IWCOL
I2CxSTAT: I2Cx STATUS REGISTER (CONTINUED)
U-0
—
R/C-0 HS
I2COV
C = Clearable bit
‘1’ = Bit is set
U-0
—
R-0 HSC
D/A
Preliminary
2
C device address byte.
2
U-0
C slave)
—
PIC24FJ128GA FAMILY
R/C-0 HSC R/C-0 HSC
U = Unimplemented bit, read as ‘0’
HS = Set in Hardware
‘0’ = Bit is cleared
P
R/C-0 HS
2
C slave)
BCL
S
R-0 HSC
GCSTAT
R-0 HSC
HSC = Hardware Set/Cleared
x = Bit is unknown
R/W
R-0 HSC
ADD10
R-0 HSC
bit 8
RBF
DS39747C-page 129
R-0 HSC
TBF
bit 0