PIC24FJ64GA006-I/PT Microchip Technology Inc., PIC24FJ64GA006-I/PT Datasheet - Page 98

• Manufacturer Part Number: PIC24FJ64GA006-I/PT
• Description: 64 PIN, 64KB FLASH, 8 KB RAM, 53 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC24FJ64GA006-I/PT

• A/d Inputs: 16 Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 16 MIPS
• Eeprom Memory: 0 Bytes
• Input Output: 53
• Interface: I2C/SPI/UART
• Memory Capacity: 64 Kbytes
• Memory Type: Flash
• Number Of Bits: 16
• Number Of Inputs: 53
• Number Of Pins: 64
• Package Type: 64-pin TQFP
• Programmable Memory: 64K Bytes
• Ram Size: 8K Bytes
• Speed: 16 MHz
• Timers: 5-16-bit
• Voltage, Range: 2-3.6 V
• Voltage, Rating: 2-3.6 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC24FJ128GA FAMILY
7.4.2
At a minimum, performing a clock switch requires this
basic sequence:
1.
2.
3.
4.
5.
Once the basic sequence is completed, the system
clock hardware responds automatically as follows:
1.
2.
3.
4.
5.
6.
DS39747C-page 96
Note 1: The processor will continue to execute
If
(OSCCON<14:12>), to determine the current
oscillator source.
Perform the unlock sequence to allow a write to
the OSCCON register high byte.
Write the appropriate value to the NOSC control
bits (OSCCON<10:8>) for the new oscillator
source.
Perform the unlock sequence to allow a write to
the OSCCON register low byte.
switch.
The clock switching hardware compares the
COSC status bits with the new value of the
NOSC control bits. If they are the same, then the
clock switch is a redundant operation. In this
case, the OSWEN bit is cleared automatically
and the clock switch is aborted.
If a valid clock switch has been initiated, the
LOCK (OSCCON<5>) and CF (OSCCON<3>)
status bits are cleared.
The new oscillator is turned on by the hardware
if it is not currently running. If a crystal oscillator
must be turned on, the hardware will wait until
the OST expires. If the new source is using the
PLL, then the hardware waits until a PLL lock is
detected (LOCK = 1).
new clock source and then performs the clock
switch.
The hardware clears the OSWEN bit to indicate a
successful clock transition. In addition, the NOSC
bit values are transferred to the COSC status bits.
The old clock source is turned off at this time,
with the exception of LPRC (if WDT or FSCM
are enabled) or SOSC (if SOSCEN remains
set).
Set the OSWEN bit to initiate the oscillator
The hardware waits for 10 clock cycles from the
2: Direct clock switches between any
desired,
OSCILLATOR SWITCHING
SEQUENCE
code throughout the clock switching
sequence. Timing sensitive code should
not be executed during this time.
Primary Oscillator mode with PLL and
FRCPLL mode are not permitted. This
applies to clock switches in either direc-
tion. In these instances, the application
must switch to FRC mode as a transition
clock source between the two PLL
modes.
read
the
COSC
bits
Preliminary
A recommended code sequence for a clock switch
includes the following:
1.
2.
3.
4.
5.
6.
7.
8.
The core sequence for unlocking the OSCCON register
and initiating a clock switch is shown in Example 7-1.
EXAMPLE 7-1:
;Place the new oscillator selection in W0
;OSCCONH (high byte) Unlock Sequence
MOV
MOV
MOV
MOV.b
MOV.b
;Set new oscillator selection
MOV.b
;OSCCONL (low byte) unlock sequence
MOV
MOV.b
MOV
MOV
MOV.b
MOV.b
;Start oscillator switch operation
MOV.b
Disable interrupts during the OSCCON register
unlock and write sequence.
Execute the unlock sequence for the OSCCON
high byte, by writing 78h and 9Ah to
OSCCON<15:8>
instructions.
Write new oscillator source to the NOSC control
bits in the instruction immediately following the
unlock sequence.
Execute the unlock sequence for the OSCCON
low
OSCCON<7:0> in two back-to-back instructions.
Set the OSWEN bit in the instruction immediately
following the unlock sequence.
Continue to execute code that is not clock
sensitive (optional).
Invoke an appropriate amount of software delay
(cycle counting) to allow the selected oscillator
and/or PLL to start and stabilize.
Check to see if OSWEN is ‘0’. If it is, the switch
was successful. If OSWEN is still set, then
check the LOCK bit to determine cause of
failure.
byte
#OSCCONH, w1
#0x78, w2
#0x9A, w3
w2, [w1]
w3, [w1]
WREG, OSCCONH
#OSCCONL, w1
#0x01, w0
#0x46, w2
#0x57, w3
w2, [w1]
w3, [w1]
w0, [w1]
by
writing
BASIC CODE SEQUENCE
FOR CLOCK SWITCHING
© 2006 Microchip Technology Inc.
in
46h
two
and
back-to-back
57h
to