PIC16C73A-04/SP Microchip Technology Inc., PIC16C73A-04/SP Datasheet - Page 72

• Manufacturer Part Number: PIC16C73A-04/SP
• Description: 28 PIN, 7 KB OTP, 192 RAM, 22 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16C73A-04/SP

• A/d Inputs: 5-Channel, 8-Bit
• Cpu Speed: 5 MIPS
• Eeprom Memory: 0 Bytes
• Input Output: 22
• Interface: I2C/SPI/USART
• Memory Type: OTP
• Number Of Bits: 8
• Package Type: 28-pin SPDIP
• Programmable Memory: 7K Bytes
• Ram Size: 192 Bytes
• Speed: 4 MHz
• Timers: 2-8-bit, 1-16-bit
• Voltage, Range: 2.5-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC16C7X
FIGURE 10-1: CCP1CON REGISTER (ADDRESS 17h)/CCP2CON REGISTER (ADDRESS 1Dh)
10.1
In Capture mode, CCPR1H:CCPR1L captures the
16-bit value of the TMR1 register when an event occurs
on pin RC2/CCP1. An event is defined as:
• Every falling edge
• Every rising edge
• Every 4th rising edge
• Every 16th rising edge
An event is selected by control bits CCP1M3:CCP1M0
(CCP1CON<3:0>). When a capture is made, the inter-
rupt request flag bit CCP1IF (PIR1<2>) is set. It must
be cleared in software. If another capture occurs before
the value in register CCPR1 is read, the old captured
value will be lost.
10.1.1
In Capture mode, the RC2/CCP1 pin should be config-
ured as an input by setting the TRISC<2> bit.
DS30390E-page 72
Note:
bit7
bit 7-6: Unimplemented: Read as '0'
bit 5-4: CCPxX:CCPxY: PWM Least Significant bits
bit 3-0: CCPxM3:CCPxM0: CCPx Mode Select bits
U-0
—
Capture Mode
CCP PIN CONFIGURATION
Applicable Devices
72 73 73A 74 74A 76 77
If the RC2/CCP1 is configured as an out-
put, a write to the port can cause a capture
condition.
Capture Mode: Unused
Compare Mode: Unused
PWM Mode: These bits are the two LSbs of the PWM duty cycle. The eight MSbs are found in CCPRxL.
0000 = Capture/Compare/PWM off (resets CCPx module)
0100 = Capture mode, every falling edge
0101 = Capture mode, every rising edge
0110 = Capture mode, every 4th rising edge
0111 = Capture mode, every 16th rising edge
1000 = Compare mode, set output on match (CCPxIF bit is set)
1001 = Compare mode, clear output on match (CCPxIF bit is set)
1010 = Compare mode, generate software interrupt on match (CCPxIF bit is set, CCPx pin is unaffected)
1011 = Compare mode, trigger special event (CCPxIF bit is set; CCP1 resets TMR1; CCP2 resets TMR1
11xx = PWM mode
U-0
—
CCPxX
R/W-0
and starts an A/D conversion (if A/D module is enabled))
CCPxY CCPxM3
R/W-0
R/W-0
CCPxM2
R/W-0
CCPxM1 CCPxM0
R/W-0
FIGURE 10-2: CAPTURE MODE
10.1.2
Timer1 must be running in timer mode or synchronized
counter mode for the CCP module to use the capture
feature. In asynchronous counter mode, the capture
operation may not work.
10.1.3
When the Capture mode is changed, a false capture
interrupt may be generated. The user should keep bit
CCP1IE (PIE1<2>) clear to avoid false interrupts and
should clear the flag bit CCP1IF following any such
change in operating mode.
RC2/CCP1
Pin
TIMER1 MODE SELECTION
SOFTWARE INTERRUPT
R/W-0
edge detect
Q’s
Prescaler
1, 4, 16
and
bit0
CCP1CON<3:0>
OPERATION BLOCK
DIAGRAM
Set flag bit CCP1IF
W = Writable bit
U = Unimplemented bit,
- n =Value at POR reset
R = Readable bit
(PIR1<2>)
1997 Microchip Technology Inc.
read as ‘0’
Capture
Enable
CCPR1H
TMR1H
CCPR1L
TMR1L