PIC16C74B-20/L Microchip Technology Inc., PIC16C74B-20/L Datasheet - Page 57

• Manufacturer Part Number: PIC16C74B-20/L
• Description: 44 PIN, 7 KB OTP, 192 RAM, 33 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16C74B-20/L

• A/d Inputs: 8-Channel, 8-Bit
• Cpu Speed: 5 MIPS
• Eeprom Memory: 0 Bytes
• Input Output: 33
• Interface: I2C/SPI/USART
• Memory Type: OTP
• Number Of Bits: 8
• Package Type: 44-pin PLCC
• Programmable Memory: 7K Bytes
• Ram Size: 192 Bytes
• Speed: 4 MHz
• Timers: 2-8-bit, 1-16-bit
• Voltage, Range: 2.5-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

REGISTER 10-2:
2000 Microchip Technology Inc.
bit 7
bit 6
bit 5
bit 4
bit 3-0
SSPCON: SYNC SERIAL PORT CONTROL REGISTER (ADDRESS 14h)
WCOL: Write Collision Flag bit
1 = The SSPBUF register was written while still transmitting the previous word (must be
0 = No collision
SSPOV: Synchronous Serial Port Overflow Flag bit
In SPI mode:
1 = A new byte was received while the SSPBUF register is still holding the previous unread
0 = No overflow
In I
1 = A byte was received while the SSPBUF register is still holding the previous unread byte.
0 = No overflow
SSPEN: Synchronous Serial Port Enable bit. When enabled, the SSP pins must be properly
configured as input or output.
In SPI mode:
1 = Enables serial port and configures SCK, SDO, and SDI as serial port pins
0 = Disables serial port and configures these pins as I/O port pins
In I
1 = Enables the serial port and configures the SDA and SCL pins as serial port pins
0 = Disables serial port and configures these pins as I/O port pins
CKP: Clock Polarity Select bit
In SPI mode:
1 = Idle state for clock is a high level (Microwire default)
0 = Idle state for clock is a low level (Microwire alternate)
In I
SCK release control
1 = Enable clock
0 = Holds clock low (clock stretch). (Used to ensure data setup time.)
SSPM3:SSPM0: Synchronous Serial Port Mode Select bits
0000 = SPI Master mode, clock = F
0001 = SPI Master mode, clock = F
0010 = SPI Master mode, clock = F
0011 = SPI Master mode, clock = TMR2 output/2
0100 = SPI Slave mode, clock = SCK pin. SS pin control enabled.
0101 = SPI Slave mode, clock = SCK pin. SS pin control disabled. SS can be used as I/O pin.
0110 = I
0111 = I
1011 = I
1110 = I
1111 = I
bit 7
Legend:
R = Readable bit
-n = Value at POR
WCOL
R/W-0
2
2
2
C mode:
C mode:
C mode:
cleared in software)
data. In case of overflow, the data in SSPSR is lost. Overflow can only occur in Slave
mode. The user must read the SSPBUF, even if only transmitting data, to avoid setting
overflow. In Master mode, the overflow bit is not set since each new reception (and trans-
mission) is initiated by writing to the SSPBUF register.
SSPOV is a "don’t care" in transmit mode. SSPOV must be cleared in software in either
mode.
2
2
2
2
2
C Slave mode, 7-bit address
C Slave mode, 10-bit address
C firmware controlled Master mode (Slave idle)
C Slave mode, 7-bit address with START and STOP bit interrupts enabled
C Slave mode, 10-bit address with START and STOP bit interrupts enabled
SSPOV
R/W-0
SSPEN
R/W-0
W = Writable bit
’1’ = Bit is set
PIC16C63A/65B/73B/74B
OSC
OSC
OSC
R/W-0
CKP
/4
/16
/64
SSPM3
R/W-0
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared
SSPM2
R/W-0
x = Bit is unknown
SSPM1
R/W-0
DS30605C-page 57
SSPM0
R/W-0
bit 0