PIC12F683-E/P Microchip Technology Inc., PIC12F683-E/P Datasheet - Page 74

• Manufacturer Part Number: PIC12F683-E/P
• Description: 8 PIN, 3.5 KB FLASH, 128 RAM, 6 I/O, PDIP
• Manufacturer: Microchip Technology Inc.

Specifications of PIC12F683-E/P

• A/d Inputs: 4 Channel, 10-Bit
• Comparators: 1
• Cpu Speed: 5 MIPS
• Eeprom Memory: 256 Bytes
• Frequency: 20 MHz
• Input Output: 6
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 8-pin PDIP
• Programmable Memory: 3.5K Bytes
• Ram Size: 128 Bytes
• Serial Interface: None
• Speed: 20 MHz
• Timers: 2-8-bit, 1-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC12F683
11.3
In Pulse Width Modulation mode, the CCP1 pin
produces up to a 10-bit resolution PWM output. Since
the CCP1 pin is multiplexed with the GPIO data latch,
the TRISIO<2> bit must be cleared to make the CCP1
pin an output.
Figure 11-3 shows a simplified block diagram of the
CCP module in PWM mode.
For a step-by-step procedure on how to set up the CCP
module for PWM operation, see Section 11.3.3
“Setup for PWM Operation”.
FIGURE 11-3:
A PWM output (Figure 11-4) has a time base (period)
and a time that the output stays high (duty cycle). The
frequency of the PWM is the inverse of the period
(1/period).
DS41211B-page 72
Note:
Note 1: The 8-bit timer is concatenated with 2-bit internal Q
CCPR1H (Slave)
Comparator
CCPR1L
Duty Cycle Registers
TMR2
PR2
Comparator
PWM Mode (PWM)
clock, or 2 bits of the prescaler, to create 10-bit time
base.
Clearing the CCP1CON register will force
the CCP1 PWM output latch to the default
low level. This is not the GPIO data latch.
(Note 1)
Clear Timer,
CCP1 pin and
latch D.C.
SIMPLIFIED PWM BLOCK
DIAGRAM
CCP1CON<5:4>
R
S
Q
TRISIO<2>
GP2/CCP1
Preliminary
FIGURE 11-4:
11.3.1
The PWM period is specified by writing to the PR2
register. The PWM period can be calculated using the
following formula.
EQUATION 11-1:
PWM frequency is defined as 1/[PWM period].
When TMR2 is equal to PR2, the following three events
occur on the next increment cycle:
• TMR2 is cleared.
• The CCP1 pin is set (Exception: If PWM duty
• The PWM duty cycle is latched from CCPR1L into
PWM Period = [(PR2) + 1] • 4 • Tosc • TMR2 Prescale Value
cycle = 0%, the CCP1 pin will not be set).
CCPR1H.
Note:
TMR2 = PR2
Duty Cycle
PWM PERIOD
The Timer2 postscaler (see Section 7.1
“Timer2 Operation”) is not used in the
determination of the PWM frequency. The
postscaler could be used to have a servo
update rate at a different frequency than
the PWM output.
Period
TMR2 = Duty Cycle
PWM OUTPUT
 2004 Microchip Technology Inc.
TMR2 = PR2