PIC12F683-E/P Microchip Technology Inc., PIC12F683-E/P Datasheet - Page 81

• Manufacturer Part Number: PIC12F683-E/P
• Description: 8 PIN, 3.5 KB FLASH, 128 RAM, 6 I/O, PDIP
• Manufacturer: Microchip Technology Inc.

Specifications of PIC12F683-E/P

• A/d Inputs: 4 Channel, 10-Bit
• Comparators: 1
• Cpu Speed: 5 MIPS
• Eeprom Memory: 256 Bytes
• Frequency: 20 MHz
• Input Output: 6
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 8-pin PDIP
• Programmable Memory: 3.5K Bytes
• Ram Size: 128 Bytes
• Serial Interface: None
• Speed: 20 MHz
• Timers: 2-8-bit, 1-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

12.3.1
The on-chip POR circuit holds the chip in Reset until
V
operation. To take advantage of the POR, simply con-
nect the MCLR pin through a resistor to V
eliminate external RC components usually needed to
create Power-on Reset. A maximum rise time for V
is required. See Section 15.0 “Electrical Specifica-
tions” for details. If the BOD is enabled, the maximum
rise time specification does not apply. The BOD
circuitry will keep the device in Reset until V
V
(BOD)”).
When the device starts normal operation (exits the
Reset condition), device operating parameters (i.e.,
voltage, frequency, temperature, etc.) must be met to
ensure operation. If these conditions are not met, the
device must be held in Reset until the operating
conditions are met.
For additional information, refer to the Application Note
AN607, “Power-up Trouble Shooting” (DS00607).
12.3.2
PIC12F683 has a noise filter in the MCLR Reset path.
The filter will detect and ignore small pulses.
It should be noted that a WDT Reset does not drive
MCLR pin low.
The behavior of the ESD protection on the MCLR pin
has been altered from early devices of this family.
Voltages applied to the pin that exceed its specification
can result in both MCLR Resets and excessive current
beyond the device specification during the ESD event.
For this reason, Microchip recommends that the MCLR
pin no longer be tied directly to V
network, as shown in Figure 12-2, is suggested.
An internal MCLR option is enabled by clearing the
MCLRE bit in the Configuration Word register. When
cleared, MCLR is internally tied to V
weak pull-up is enabled for the MCLR pin. In-Circuit
Serial Programming is not affected by selecting the
internal MCLR option.
 2004 Microchip Technology Inc.
DD
BOD
Note:
has reached a high enough level for proper
(see
POWER-ON RESET
The POR circuit does not produce an
internal Reset when V
re-enable the POR, V
for a minimum of 100 s.
MCLR
Section 12.3.4
“Brown-out
DD
DD
. The use of an RC
DD
DD
must reach Vss
and an internal
declines. To
DD
DD
. This will
reaches
Detect
Preliminary
DD
FIGURE 12-2:
12.3.3
The Power-up Timer provides a fixed 64 ms (nominal)
time-out on power-up only, from POR or Brown-out
Detect. The Power-up Timer operates from the 31 kHz
LFINTOSC oscillator. For more information, see
Section 3.4 “Internal Clock Modes”. The chip is kept
in Reset as long as PWRT is active. The PWRT delay
allows the V
uration bit, PWRTE, can disable (if set) or enable (if
cleared or programmed) the Power-up Timer. The
Power-up Timer should be enabled when Brown-out
Detect is enabled, although it is not required.
The Power-up Timer delay will vary from chip-to-chip
and vary due to:
• V
• Temperature variation
• Process variation
See DC parameters for details (Section 15.0 “Electrical
Specifications”).
DD
variation
V
DD
R1
1 k
POWER-UP TIMER (PWRT)
C1
0.1 F
(optional, not critical)
DD
to rise to an acceptable level. A config-
or greater)
RECOMMENDED MCLR
CIRCUIT
PIC12F683
MCLR
PIC12F683
DS41211B-page 79