DS2181A+ Maxim Integrated Products, DS2181A+ Datasheet - Page 23

• Manufacturer Part Number: DS2181A+
• Description: IC TXRX CEPT PRIMARY RATE 40-DIP
• Manufacturer: Maxim Integrated Products
• Type: Transceiverr

Specifications of DS2181A+

• Number Of Drivers/receivers: 1/1
• Protocol: CEPT
• Voltage - Supply: 4.5 V ~ 5.5 V
• Mounting Type: Through Hole
• Package / Case: 40-DIP (0.600", 15.24mm)
• Logic Type: CMOS
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 4.5 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: Through Hole
• High Level Output Current: - 1 mA
• Interface: DMA, CPI
• Low Level Output Current: 4 mA
• Minimum Operating Temperature: 0 C
• Output Current: 4 mA
• Supply Current: 5 mA
• Supply Voltage Range: 4.5V To 5.5V
• Logic Case Style: LCC
• No. Of Pins: 44
• Operating Temperature Range: 0°C To +70°C
• Termination Type: SMD
• Transceiver Type: Network
• Driver Case Style: LCC
• Rohs Compliant: Yes
• Filter Terminals: SMD
• Interface Type: Serial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

DS2181A
RDMA
RDMA transitions high when bit 6 of timeslot 16 in frame 0 is set for three consecutive occasions and
returns low when the bit is clear for three consecutive occasions. The RDMA bit (RSR.6) is a latched
version of the RDMA output.
RCL
RCL transitions high after 32 consecutive 0s appear at RPOS and RNEG; it goes low at the next 1
occurrence.
RFER
The RFER output transitions high when received frame alignment, CAS multiframe alignment and/or
CRC4 code words are in error. The FECR and CECR log error events reported at this output. FECR logs
only the frame alignment word errors. CECR logs CRC4 code word errors.
To complement the on-chip error logging capabilities of the DS2181A, the system designer can use off-
chip logic gated by receive side outputs RCHCLK, RAF, RSTS and RCSYNC to demux error states
present at RFER. See the separate DS2181A CEPT Transceiver Application Note for more details.
RFER OUTPUT TIMING FOR ALL ERROR CONDITIONS Figure 23
CAS MULTIFRAME ALIGNMENT ERROR Figure 24
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