PIC16C711-04/P Microchip Technology Inc., PIC16C711-04/P Datasheet - Page 31

• Manufacturer Part Number: PIC16C711-04/P
• Description: 18 PIN, 1.75 KB OTP, 68 RAM, 13 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16C711-04/P

• A/d Inputs: 4-Channel, 8-Bit
• Cpu Speed: 5 MIPS
• Eeprom Memory: 0 Bytes
• Input Output: 13
• Memory Type: OTP
• Number Of Bits: 8
• Package Type: 18-pin PDIP
• Programmable Memory: 1.75K Bytes
• Ram Size: 68 Bytes
• Speed: 20 MHz
• Timers: 1-8-bit
• Voltage, Range: 2.5-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

6.0
The Timer0 module timer/counter has the following fea-
tures:
• 8-bit timer/counter
• Readable and writable
• 8-bit software programmable prescaler
• Internal or external clock select
• Interrupt on overflow from FFh to 00h
• Edge select for external clock
Figure 6-1 is a simplified block diagram of the Timer0
module.
Timer mode is selected by clearing bit T0CS
(OPTION<5>). In timer mode, the Timer0 module will
increment every instruction cycle (without prescaler). If
the TMR0 register is written, the increment is inhibited
for the following two instruction cycles (Figure 6-2 and
Figure 6-3). The user can work around this by writing
an adjusted value to the TMR0 register.
Counter mode is selected by setting bit T0CS
(OPTION<5>). In counter mode, Timer0 will increment
either on every rising or falling edge of pin RA4/T0CKI.
The incrementing edge is determined by the Timer0
Source Edge Select bit T0SE (OPTION<4>). Clearing
FIGURE 6-1:
FIGURE 6-2:
Applicable Devices
1997 Microchip Technology Inc.
RA4/T0CKI
pin
Instruction
TMR0
PC
(Program
Counter)
Fetch
Instruction
Executed
Note 1: T0CS, T0SE, PSA, PS2:PS0 (OPTION<5:0>).
TIMER0 MODULE
2: The prescaler is shared with Watchdog Timer (refer to Figure 6-6 for detailed block diagram).
T0SE
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
T0
F
TIMER0 BLOCK DIAGRAM
TIMER0 TIMING: INTERNAL CLOCK/NO PRESCALE
OSC
PC-1
/4
710 71 711 715
MOVWF TMR0
T0+1
T0CS
PC
0
1
MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W
PS2, PS1, PS0
Write TMR0
executed
T0+2
Programmable
PC+1
Prescaler
3
NT0
Read TMR0
reads NT0
PC+2
PSA
1
0
bit T0SE selects the rising edge. Restrictions on the
external clock input are discussed in detail in
Section 6.2.
The prescaler is mutually exclusively shared between
the Timer0 module and the Watchdog Timer. The pres-
caler assignment is controlled in software by control bit
PSA (OPTION<3>). Clearing bit PSA will assign the
prescaler to the Timer0 module. The prescaler is not
readable or writable. When the prescaler is assigned to
the Timer0 module, prescale values of 1:2, 1:4, ...,
1:256 are selectable. Section 6.3 details the operation
of the prescaler.
6.1
The TMR0 interrupt is generated when the TMR0 reg-
ister overflows from FFh to 00h. This overflow sets bit
T0IF (INTCON<2>). The interrupt can be masked by
clearing bit T0IE (INTCON<5>). Bit T0IF must be
cleared in software by the Timer0 module interrupt ser-
vice routine before re-enabling this interrupt. The
TMR0 interrupt cannot awaken the processor from
SLEEP since the timer is shut off during SLEEP. See
Figure 6-4 for Timer0 interrupt timing.
PSout
Read TMR0
reads NT0
NT0
PC+3
(2 cycle delay)
Sync with
Timer0 Interrupt
Internal
clocks
MOVF TMR0,W
Read TMR0
reads NT0
NT0
PC+4
PSout
PIC16C71X
MOVF TMR0,W
Read TMR0
reads NT0 + 1
NT0+1
Data bus
TMR0
PC+5
8
DS30272A-page 31
Set interrupt
Read TMR0
reads NT0 + 2
flag bit T0IF
on overflow
NT0+2
PC+6
T0