PIC16F916-I/SO Microchip Technology Inc., PIC16F916-I/SO Datasheet - Page 189
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PIC16F916-I/SO
Manufacturer Part Number
PIC16F916-I/SO
Description
28 PIN, 14 KB FLASH, 352 RAM, 25 I/O
Manufacturer
Microchip Technology Inc.
Datasheet
1.PIC16F916-ISO.pdf
(272 pages)
Specifications of PIC16F916-I/SO
A/d Inputs
5-Channel, 10-Bit
Comparators
2
Cpu Speed
5 MIPS
Eeprom Memory
256 Bytes
Input Output
25
Interface
I2C/SPI/USART
Memory Type
Flash
Number Of Bits
8
Package Type
28-pin SOIC
Programmable Memory
14K Bytes
Ram Size
352 Bytes
Speed
20 MHz
Timers
2-8-bit, 1-16-bit
Voltage, Range
2-5.5 V
Lead Free Status / Rohs Status
RoHS Compliant part
Electrostatic Device
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC16F916-I/SO
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
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16.2
The PIC16F917/916/914/913 differentiates between
various kinds of Reset:
a)
b)
c)
d)
e)
f)
Some registers are not affected in any Reset condition;
their status is unknown on POR and unchanged in any
other Reset. Most other registers are reset to a “Reset
state” on:
• Power-on Reset
• MCLR Reset
• MCLR Reset during Sleep
• WDT Reset
• Brown-out Reset (BOR)
FIGURE 16-1:
© 2005 Microchip Technology Inc.
MCLR/V
Power-on Reset (POR)
WDT Reset during normal operation
WDT Reset during Sleep
MCLR Reset during normal operation
MCLR Reset during Sleep
Brown-out Reset (BOR)
CLKI pin
OSC1/
V
Note 1:
DD
Reset
PP
pin
LFINTOSC
OST/PWRT
Refer to the Configuration Word register (Register 16-1).
Brown-out
V
Module
DD
Detect
WDT
Reset
SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
Rise
OST
PWRT
(1)
10-bit Ripple Counter
WDT
Time-out
Reset
11-bit Ripple Counter
SBOREN
BOREN
Power-on Reset
External
Reset
SLEEP
Preliminary
PIC16F917/916/914/913
They are not affected by a WDT wake-up since this is
viewed as the resumption of normal operation. TO and
PD bits are set or cleared differently in different Reset
situations, as indicated in Table 16-2. These bits are
used in software to determine the nature of the Reset.
See Table 16-5 for a full description of Reset states of
all registers.
A simplified block diagram of the On-Chip Reset Circuit
is shown in Figure 16-1.
The MCLR Reset path has a noise filter to detect and
ignore small pulses. See Section 19.0 “Electrical
Specifications” for pulse width specifications.
Enable PWRT
Enable OST
S
R
DS41250E-page 187
Q
Chip_Reset
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