PIC32MX564F128LT-I/BG Microchip Technology Inc., PIC32MX564F128LT-I/BG Datasheet - Page 91
PIC32MX564F128LT-I/BG
Manufacturer Part Number
PIC32MX564F128LT-I/BG
Description
121 XBGA 10X10X1.20MM T/R, 100 PINS, 128KB FLASH, 32KB RAM, 80 MHZ, USB, CAN, 4
Manufacturer
Microchip Technology Inc.
Datasheet
1.PIC32MX795F512H-80IPT.pdf
(254 pages)
Specifications of PIC32MX564F128LT-I/BG
A/d Inputs
16-Channel, 10-Bit
Comparators
2
Eeprom Memory
0 Bytes
Input Output
85
Interface
CAN/I2C/SPI/UART/USB
Memory Type
Flash
Number Of Bits
32
Package Type
100-pin XBGA
Programmable Memory
128K Bytes
Ram Size
32K Bytes
Speed
80 MHz
Temperature Range
–40 to +85 °C
Timers
5-16-bit
Voltage, Range
2.3-3.6 V
Lead Free Status / Rohs Status
RoHS Compliant part
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC32MX564F128LT-I/BG
Manufacturer:
Microchip Technology
Quantity:
10 000
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TABLE 4-22:
TABLE 4-23:
Legend:
Note
Legend:
Note
F400 NVMCON
F410
F420 NVMADDR
F430 NVMDATA
F440
F000 OSCCON
F010
0000 WDTCON
F600
F610 RSWRST
F230
1:
1:
OSCTUN
SYSKEY
NVMKEY
NVMSRC
2:
RCON
ADDR
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
This register has corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See
information.
Reset values are dependent on the DEVCFGx Configuration bits and the type of Reset.
(1)
(1)
31:16
31:16
31:16
31:16
31:16
31:16
15:0
15:0
15:0
15:0
15:0
15:0
31:16
31:16
31:16
31:16
31:16
15:0
15:0
15:0
15:0
15:0
FLASH CONTROLLER REGISTER MAP
SYSTEM CONTROL REGISTER MAP
31/15
31/15
ON
—
—
—
—
—
—
—
—
—
WR
—
30/14
WREN
30/14
—
—
—
—
—
—
—
—
—
—
COSC<2:0>
29/13
WRERR
29/13
—
—
—
—
—
—
—
—
—
PLLODIV<2:0>
LVDERR
28/12
28/12
—
—
—
—
—
—
—
—
—
LVDSTAT
27/11
27/11
—
—
—
—
—
—
—
—
—
—
(1,2)
26/10
26/10
—
—
—
—
—
—
—
—
—
—
FRCDIV<2:0>
NOSC<2:0>
CMR
25/9
25/9
—
—
—
—
—
—
—
—
—
NVMSRCADDR<31:0>
VREGS
NVMADDR<31:0>
24/8
NVMDATA<31:0>
SYSKEY<31:0>
NVMKEY<31:0>
24/8
—
—
—
—
—
—
—
—
—
Bits
Bits
CLKLOCK
EXTR
23/7
23/7
—
—
—
—
—
—
—
—
—
—
SOSCRDY
ULOCK
22/6
SWR
22/6
—
—
—
—
—
—
—
—
SLOCK
21/5
21/5
Section 12.1.1 “CLR, SET and INV Registers”
—
—
—
—
—
—
—
—
—
SWDTPS<4:0>
SLPEN
WDTO
20/4
20/4
—
—
—
—
—
—
—
Section 12.1.1 “CLR, SET and INV Registers”
PBDIV<1:0>
SLEEP
19/3
19/3
CF
—
—
—
—
—
—
TUN<5:0>
UFRCEN
IDLE
18/2
18/2
—
—
—
—
—
—
NVMOP<3:0>
PLLMULT<2:0>
SOSCEN
for more information.
17/1
17/1
BOR
—
—
—
—
—
—
—
WDTCLR 0000
OSWEN
SWRST
16/0
16/0
POR
for more
—
—
—
—
—
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
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