ATA6836-PXSY Atmel, ATA6836-PXSY Datasheet - Page 7

• Manufacturer Part Number: ATA6836-PXSY
• Description: MOSFET & Power Driver ICs Hex Half Bridge Driver
• Manufacturer: Atmel

Specifications of ATA6836-PXSY

• Product: Half-Bridge Drivers
• Mounting Style: SMD/SMT
• Package / Case: QFN-24

3. Functional Description
3.1
Figure 3-1.
4952J–AUTO–03/11
CLK
DO
CS
Serial Interface
DI
Data Transfer Input Data Protocol
0
SRR
TP
1
SLS1
LS1
Data transfer starts with the falling edge of the CS signal. Data must appear at DI synchro-
nized to CLK and is accepted on the falling edge of the CLK signal. LSB (bit 0, SRR) has to be
transferred first. Execution of new input data is enabled on the rising edge of the CS signal.
When CS is high, pin DO is in a tri-state condition. This output is enabled on the falling edge of
CS. Output data will change their state with the rising edge of CLK and stay stable until the
next rising edge of CLK appears. LSB (bit 0, TP) is transferred first.
Table 3-1.
SHS1
2
HS1
Bit
10
11
12
13
14
15
0
1
2
3
4
5
6
7
8
9
SLS2
3
LS2
Input Register
SHS2
4
HS2
Input Data Protocol
SRR
HS1
HS2
HS3
HS4
HS5
HS6
OLD
SCT
LS1
LS2
LS3
LS4
LS5
LS6
SI
5
SLS3
LS3
6
SHS3
HS3
Controls output LS1 (high = switch output LS1 on)
Controls output HS1 (high = switch output HS1 on)
See LS1
See LS1
See LS1
See LS1
Function
Status register reset (high = reset; the bits PSF, SCD and
overtemperature shutdown in the output data register are set to low)
See HS1
See HS1
See HS1
See HS1
See LS1
See HS1
Open load detection (low = on)
Programmable time delay for short circuit
(shutdown delay high/low = 12ms/1.5ms)
Software inhibit; low = standby, high = normal operation
(data transfer is not affected by standby function because the digital
part is still powered)
7
SLS4
LS4
SHS4
8
HS4
9
SLS5
LS5
10
SHS5
HS5
11
SLS6
LS6
12
SHS6
HS6
Atmel ATA6836
13
OLD
SCD
14
INH
SCT
15
PSF
SI
7