71M6541F-IGT/F Maxim Integrated Products, 71M6541F-IGT/F Datasheet - Page 17

• Manufacturer Part Number: 71M6541F-IGT/F
• Description: PMIC Solutions Precision Energy Meter IC
• Manufacturer: Maxim Integrated Products
• Type: Metering SoCr

Specifications of 71M6541F-IGT/F

• Core: 8051
• Core Architecture: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 5 KB
• Device Million Instructions Per Second: 5 MIPS
• Interface Type: I2C, ICE, SPI, UART
• Maximum Clock Frequency: 5 MHz
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Number Of Programmable I/os: 30
• Number Of Timers: 2
• On-chip Adc: 22 bit
• Operating Supply Voltage: 3 V to 3.6 V
• Package / Case: LQFP-64
• Processor Series: 8051
• Program Memory Size: 64 KB
• Program Memory Type: Flash
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

For both multiplexer sequences shown in
(where CK32 = 32768 Hz), therefore, the resulting sample rate is 32768 Hz / 13 = 2520.6 Hz.
Table 3
Multiplexer advance, FIR initiation and chopping of the ADC reference voltage (using the internal CROSS
signal, see
v1.1
IAP
IAN
IBP
IBN
Pin
VA
VB
summarizes the various AFE input configurations.
2.2.7 Voltage
Channel
ADC10
ADC0
ADC1
ADC2
ADC3
ADC9
ADC
MUX STATE
MUX STATE
MUX_SYNC
MUX_SYNC
Fig. 4:
Fig. 2:
Fig. 3:
Fig. 5:
CROSS
CROSS
Figure 6: States in a Multiplexer Frame (MUX_DIV[3:0] = 3)
Figure 7: States in a Multiplexer Frame (MUX_DIV[3:0] = 4)
CK32
CK32
DIFFA_E = 1
DIFFB_E = 1
RMT_E = 1
Required
References) are controlled by the internal MUX_CTRL circuit. Additionally,
Setting
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S
S
or
--
--
Table 3: ADC Input Configuration
IA
0
IA
IA
IA
Comment
Differential mode must be selected with DIFFA_E = 1 (I/O
RAM 0x210C[4]). The ADC results are stored in CE RAM
location ADC0 (CE RAM 0x0), and ADC1 (CE RAM 0x1) is not
disturbed.
For locally connected sensors
differential input must be enabled by setting DIFFB_E (I/O
RAM 0x210C[5].
For the remote connected sensor
with a remote shunt sensor, RMT_E (I/O RAM 0x2709[3])
must be set.
In both cases, the ADC results are stored in RAM location
ADC2 (CE RAM 0x2), and ADC3 (CE RAM 0x3) is not
disturbed.
Single-ended mode only. The ADC result is stored in RAM
location ADC10 (CE RAM 0xA).
Single-ended mode only (71M6542F only). The ADC result
is stored in RAM location ADC9 (CE RAM 0x9).
0 0
Figure 6
MUX_DIV[3:0] = 3 Conversions
MUX_DIV = 4 Conversions
VA
Multiplexer Frame
1
Multiplexer Frame
and
VA
VA
VA
Figure
1
IB
2
7, the frame duration is 13 CK32 cycles
Not Used
(Figure 2
IB
VB
2
VB
3
(Figure 3
11/5/2010
11/5/2010
Settle
and
Settle
S
S
and
Figure
Figure
0
0
4), the
5)
17