71M6542F-IGT/F Maxim Integrated Products, 71M6542F-IGT/F Datasheet
71M6542F-IGT/F
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71M6542F-IGT/F Summary of contents
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... The 71M6541D/71M6541F/71M6542F support optional interfaces to the Teridian 71M6x01 series of isolated sensors, which offer BOM cost reduction, immunity to magnetic tamper, and enhanced reliability. Other features include an SPI™ interface, advanced ...
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Introduction ................................................................................................................................. 10 2 Hardware Description .................................................................................................................. 11 2.1 Hardware Overview............................................................................................................... 11 2.2 Analog Front End (AFE) ........................................................................................................ 12 2.2.1 Signal Input Pins ....................................................................................................... 14 2.2.2 Input Multiplexer ........................................................................................................ 15 2.2.3 Delay Compensation ................................................................................................. 19 2.2.4 ADC Pre-Amplifier ..................................................................................................... ...
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... Using Local Sensors ........................................................................................ 93 4.4 71M6541D/F Using 71M6x01and Current Shunts .................................................................. 94 4.5 71M6542F Using Local Sensors ............................................................................................ 95 4.6 71M6542F Using 71M6x01 and Current Shunts .................................................................... 96 4.7 Metrology Temperature Compensation .................................................................................. 97 4.7.1 Voltage Reference Precision ..................................................................................... 97 4.7.2 Temperature Coefficients for the 71M654x ................................................................ 97 4.7.3 Temperature Compensation for VREF with Local Sensors ......................................... 98 4 ...
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... LQFP Outline Package Drawing ................................................................... 153 6.6.2 100-Pin LQFP Package Outline Drawing ................................................................. 154 6.7 Pinout Diagrams ................................................................................................................. 155 6.7.1 71M6541D/F LQFP-64 Package Pinout ................................................................... 155 6.7.2 71M6542F LQFP-100 Package Pinout..................................................................... 156 6.8 Pin Descriptions .................................................................................................................. 157 6.8.1 Power and Ground Pins........................................................................................... 157 6.8.2 Analog Pins ............................................................................................................. 158 6 ...
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... Figure 1: IC Functional Block Diagram ..................................................................................................... 9 Figure 2. 71M6541D/F AFE Block Diagram (Local Sensors) .................................................................. 12 Figure 3. 71M6541D/F AFE Block Diagram with 71M6x01 ..................................................................... 13 Figure 4. 71M6542F AFE Block Diagram (Local Sensors) ...................................................................... 13 Figure 5. 71M6542F AFE Block Diagram with 71M6x01 ......................................................................... 14 Figure 6: States in a Multiplexer Frame (MUX_DIV[3: .................................................................. 17 Figure 7: States in a Multiplexer Frame (MUX_DIV[3: .................................................................. 17 Figure 8: General Topology of a Chopped Amplifier ...
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... Table 49: Data/Direction Registers for SEGDIO0 to SEGDIO14 (71M6541D/F)...................................... 61 Table 50: Data/Direction Registers for SEGDIO19 to SEGDIO27 (71M6541D/F).................................... 62 Table 51: Data/Direction Registers for SEGDIO36-39 to SEGDIO44-45 (71M6541D/F) .......................... 62 Table 52: Data/Direction Registers for SEGDIO51 and SEGDIO55 (71M6541D/F) ................................. 62 Table 53: Data/Direction Registers for SEGDIO0 to SEGDIO15 (71M6542F) ......................................... 63 6 © 2008–2011 Teridian Semiconductor Corporation v1.1 ...
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... Table 56: Data/Direction Registers for SEGDIO51 to SEGDIO55 (71M6542F) ....................................... 64 Table 57: LCD_VMODE[1:0] Configurations .......................................................................................... 65 Table 58: LCD Configurations ............................................................................................................... 67 Table 59: 71M6541D/F LCD Data Registers for SEG46 to SEG50 ......................................................... 69 Table 60: 71M6542F LCD Data Registers for SEG46 to SEG50 ............................................................ 70 Table 61: EECTRL Bits for 2-pin Interface ............................................................................................... 71 Table 62: EECTRL Bits for the 3-wire Interface ....................................................................................... 71 Table 63: SPI Transaction Fields ........................................................................................................... 74 Table 64: SPI Command Sequences ...
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Table 107: PLL Performance Specifications ......................................................................................... 144 Table 108: LCD Driver Performance Specifications .............................................................................. 145 Table 109: LCD Driver Performance Specifications .............................................................................. 146 Table 110: VREF Performance Specifications ...................................................................................... 148 Table 111. ADC Converter Performance Specifications ....................................................................... 149 Table 112: ...
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IAP IAN IBP VBIAS MUX IBN and PREAMP VREF VA VB* MUX CROSS MUX CTRL CK32 RTCLK (32KHz) XIN Oscillator XOUT 32 KHz 4.9 MHz CK_4X CLOCK GEN CKMPU_2x MUX_SYNC CKCE < 4.9MHz TEST TEST MODE CE CONTROL CKMPU < ...
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... Introduction This data sheet covers the 71M6541D (32KB), 71M6541F (64KB) and 71M6542F (64KB) fourth generation Teridian energy measurement SoCs. The term “71M654x” is used when discussing a device feature or behavior that is applicable to all three part numbers. The appropriate part number is indicated when a device feature or behavior is being discussed that applies only to a specific part number. This data sheet also covers basic details about the companion 71M6x01 isolated current sensor device ...
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... These measurements are then accessed by the MPU, processed further and output using the peripheral devices available to the MPU. In addition to advanced measurement functions, the clock function allows the 71M6541D/F and 71M6542F to record time-of-use (TOU) metering information for multi-rate applications and to time-stamp tamper or other events ...
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One of the two internal UARTs is adapted to support ...
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... Figure 3. 71M6541D/F AFE Block Diagram with 71M6x01 Figure 4 shows the 71M6542F AFE with locally connected sensors. The analog input signals (IAP-IAN, VA, IBP-IBN and VB) are multiplexed to the ADC input and sampled by the ADC. The ADC output is decimated by the FIR filter and stored in CE RAM where it can be accessed and processed by the CE. ...
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... In the case of Current Transformers (CT), the current is measured as a voltage across a burden resistor that is connected to the secondary winding of the CT. Meanwhile, line voltages are sensed through resistive voltage dividers. The VA and VB pins (VB is available in the 71M6542F only) are single-ended and their common return is the V3P3A pin. ...
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... The multiplexer always starts at state 1 and proceeds until as many states as determined by MUX_DIV[3:0] have been converted. The 71M6541D/F and 71M6542F each require a unique CE code that is written for the specific application. Moreover, each CE code requires specific AFE and MUX settings in order to function properly. ...
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... VA voltage is precisely known so that delay compensation can be properly applied. The 71M6542F adds the ability to sample a second phase voltage (applied at the VB pin), which makes it suitable for meters with two voltage and two current sensors, such as meters implementing Equation 2 for dual-phase operation (P = VA*IA+VB*IB) ...
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... In both cases, the ADC results are stored in RAM location ADC2 (CE RAM 0x2), and ADC3 (CE RAM 0x3) is not disturbed. Single-ended mode only. The ADC result is stored in RAM location ADC10 (CE RAM 0xA). Single-ended mode only (71M6542F only). The ADC result is stored in RAM location ADC9 (CE RAM 0x9). Settle 2 S ...
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... MUX3_SEL[3:0] control fields must be written with a valid ADC handle that is not being used. Typically, ADC1 is used for this purpose (see 71M6541D/F or 71M6542F, is used as a place holder in the multiplexer frame, in order to generate the correct multiplexer frame sequence and the correct sample rate. The resulting sample data stored in CE RAM 0x1 is undefined and is ignored by the CE code ...
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Table 4 summarizes the I/O RAM registers used for configuring the multiplexer, signals pins, and ADC. All listed registers are 0 after reset and wake from battery modes, and are readable and writable. Table 4: Multiplexer and ADC Configuration Bits ...
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The residual phase error is negligible, and is typically less than ±1.5 milli-degrees at 100Hz, thus it does not ...
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V inp V inn CROSS Figure 8: General Topology of a Chopped Amplifier It is assumed that an offset voltage Voff appears at the positive amplifier input. With all switches, as controlled by CROSS (an internal signal), in the A ...
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... One 71M6x01 Isolated Sensor can be supported by the 71M6541D/F and 71M6542F. When remote interface IBP-IBN is enabled, the two analog current inputs pins IBP and IBN become a digital balanced differential interface to the remote sensor ...
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Reserved Notes: 1. Only two codes of RCMD[4:2] (SFR 0xFC[4:2]) are relevant for normal operation. These are RCMD[4:2] = 001 and 010. Codes 000 and 101 are invalid and will be ignored if used. The remaining codes are reserved ...
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RST Name Address Default TMUXRB[2:0] 270A[2:0] 000 RMT_RD[15:8] 2602[7:0] RMT_RD[7:0] 2603[7:0] RFLY_DIS 210C[3] RMTB_E 2709[3] Refer to Table 76 starting on page 2.3 Digital Computation Engine (CE) The CE, a dedicated 32-bit signal processor, performs the precision computations necessary to ...
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... No 2.3.4 Meter Equations The 71M6541D/F and 71M6542F provide hardware assistance to the CE in order to support various meter equations. This assistance is controlled through I/O RAM register EQU[2:0] (equation assist). The Compute Engine (CE) firmware for industrial configurations can implement the equations listed in specifies the equation to be used based on the meter configuration and on the number of phases used for metering ...
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CK32 MUX_SYNC MUX_STATE CKTEST RTM FLAG RTM DATA0 (32 bits) RTM DATA1 (32 bits) RTM DATA2 (32 bits) RTM DATA3 (32 bits) ADC TIMING CK32 150 MUX_SYNC MUX STATE S 0 ADC EXECUTION CE TIMING 0 ...
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... Pulse Generators The 71M6541D/F and 71M6542F provide four pulse generators, VPULSE, WPULSE, XPULSE and YPULSE, as well as hardware support for the VPULSE and WPULSE pulse generators. The pulse generators can be used to output CE status indicators, SAG for example, to DIO pins. All pulses can be configured to generate interrupts to the MPU ...
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... CK_FIR clock cycles based on the pulse interval T MAX PLS_MAXWIDTH[7: MAX ADC MUX Frame MUX_DIV Conversions (MUX_DIV=4 is shown) W_FIFO 4*PLS_INTERVAL 4*PLS_INTERVAL Figure 3. The ADCs (i.e., ADC in the 71M654x and the ADC in (71M6542F) show the sampling sequence when both current I I Settle 4*PLS_INTERVAL 4*PLS_INTERVAL Figure 2. However, when the IB v1.1 5 ...
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... VB voltage sample. As with the 71M6541D/F, IA samples are obtained from a current sensor that is directly connected to the 71M6542F, while IB samples may be obtained from a directly connected remotely connected shunt using a 71M6x01 isolated device as seen in The number of samples processed during one accumulation cycle is controlled by the I/O RAM register SUM_SAMPS[12:0] (I/O RAM 0x2107[4:0], 0x2108[7:0]) ...
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IA 122.07 µs CK32 (32768 Hz) MUX STATE S 0 Figure 14: Samples from Multiplexer Cycle (MUX_DIV[3: 91.5 µs CK32 (32768 Hz) MUX STATE S 0 Figure 15: Samples from Multiplexer Cycle (MUX_DIV[3: © ...
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... MPU Core The 71M6541D/F and 71M6542F include an 80515 MPU (8-bit, 8051-compatible) that processes most instructions in one clock cycle. Using a 4.9 MHz clock results in a processing throughput of 4.9 MIPS. The 80515 architecture eliminates redundant bus states and implements parallel execution of fetch and execution phases ...
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The 80515 writes into external data memory when the MPU executes a MOVX @Ri,A or MOVX @DPTR,A instruction. The MPU reads external data memory by executing a MOVX A,@Ri or MOVX A,@DPTR instruction (PDATA, SFR 0xBF, provides the upper 8 ...
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An alternative data pointer is available in the form of the PDATA register (SFR 0xBF), sometimes referred to as USR2). It defines the high byte of a 16-bit address when reading or writing XDATA with the instruction MOVX A,@Ri or ...
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Generic 80515 Special Function Registers Table 13 shows the location, description and reset or power-up value of the generic 80515 SFRs. Additional descriptions of the registers can be found at the page numbers listed in the table. Table 13: ...
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Accumulator (ACC, A, SFR 0x E0): ACC is the accumulator register. Most instructions use the accumulator to hold the operand. The mnemonics for accumulator-specific instructions refer to accumulator as A, not ACC. B Register (SFR 0xF0): The B register is ...
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... The three low order bits of the CKCON[2:0] (SFR 0x8E) register define the stretch memory cycles that are used for MOVX instructions when accessing external peripherals. The practical value of this register for the 71M6541D/F and 71M6542F is to guarantee access to XRAM between CE, MPU, and SPI. The default setting of CKCON[2:0] (001) should not be changed. ...
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UART0 RX: Serial input data are applied at this pin. Conforming to RS-232 standard, the bytes are input LSB first. • UART0 TX: This pin is used to output the serial data. The bytes are output LSB first. Several ...
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UART Control Registers: The functions of UART0 and UART1 depend on the setting of the Serial Port Control Registers S0CON and S1CON shown in Table 19 and Since the TI0, RI0, TI1 and RI1 bits are in an SFR bit ...
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Table 21: PCON Register Bit Description (SFR 0x87) Bit Symbol Function The SMOD bit doubles the baud rate when set PCON[7] SMOD 2.4.6 Timers and Counters The 80515 has two 16-bit timer/counter registers: Timer 0 and Timer 1. These registers ...
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Table 24: TMOD Register Bit Description (SFR 0x89) Bit Symbol Function Timer/Counter 1 If TMOD[7] is set, external input signal control is enabled for Counter 1. The TMOD[7] Gate TR1 bit in the TCON register (SFR 0x88) must also be ...
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IEN0 (SFR 0xA8), IEN1 (SFR 0xB8), and IEN2 (SFR 0x9A). Figure 16 shows the device interrupt structure. Referring to Figure 16, interrupt sources ...
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IEN1[2] EX3 IEN1[1] EX2 IEN1[0] – Table 28: The IEN2 Bit Functions (SFR 0x9A) Bit Symbol IEN2[0] ES1 Table 29: TCON Bit Functions (SFR 0x88) Bit Symbol TCON[7] TF1 TCON[6] TR1 TCON[5] TF0 TCON[4] TR0 TCON[3] IE1 TCON[2] IT1 TCON[1] ...
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IRCON[1] IEX2 IRCON[0] – TF0 and TF1 (Timer 0 and Timer 1 overflow flags) are automatically cleared by hardware when the service routine is called (Signals T0ACK and T1ACK – port ISR – active high when the service routine is ...
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External MPU Interrupts The seven external interrupts are the interrupts external to the 80515 core, i.e., signals that originate in other parts of the 71M654x, for example the CE, DIO, RTC, or EEPROM interface. The external interrupts are connected as ...
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Interrupt Enable Name Location EX_SPI 0x2701[7] EX_EEX 0x2700[7] EX_XPULSE 0x2700[6] EX_YPULSE 0x2700[5] 0x2701[6] EX_WPULSE EX_VPULSE 0x2701[5] Interrupt Priority Level Structure All interrupt sources are combined in groups, as shown in Table 34: Interrupt Priority Level Groups Group 0 External interrupt ...
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Interrupt Sources and Vectors Table 38 shows the interrupts with their associated flags and vector addresses. Interrupt Request Flag IE0 TF0 IE1 TF1 RI0/TI0 RI1/TI1 IEX2 IEX3 IEX4 IEX5 IEX6 46 © 2008–2011 Teridian Semiconductor Corporation Table 37: Interrupt Polling ...
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... Physical Memory 2.5.1.1 Flash Memory The device includes 64 (71M6542F, 71M6541F (71M6541D) of on-chip flash memory. The flash memory primarily contains MPU and CE program code. It also contains images of the CE RAM and I/O RAM. On power-up, before enabling the CE, the MPU copies these images to their respective locations. ...
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... Write operations to page zero, whether by MPU or ICE are inhibited. The 71M6541D/F and 71M6542F also include hardware to protect against unintentional Flash write and erase. To enable flash write and erase operations, a 4-bit hardware key that must be written to the FLSH_UNLOCK[3:0] field. The key is the binary number ‘0010’. If FLSH_UNLOCK[3:0] is not ‘0010’, the Flash erase and write operation is inhibited by hardware. Proper operation of this security key requires that there be no firmware function that writes ‘ ...
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... The 71M6541D includes static RAM memory on-chip (XRAM) plus 256 bytes of internal RAM in the MPU core. The 71M6541D/F and the 71M6542F include static RAM memory on-chip (XRAM) plus 256 bytes of internal RAM in the MPU core. The static RAM is used for data storage for both MPU and CE operations ...
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Derived Clock From OSC Crystal MCK Crystal/PLL CKCE MCK CKADC MCK CKMPU MCK CKICE MCK CKOPTMOD MCK CK32 MCK 2.5.4 Real-Time Clock (RTC) 2.5.4.1 RTC General Description The RTC is driven directly by the crystal oscillator and is powered by ...
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Name Location RTC_ADJ[6:0] 2504[6:0] RTC_P[16:14] 289B[2:0] RTC_P[13:6] 289C[7:0] RTC_P[5:0] 289D[7:2] RTC_Q[1:0] 289D[1:0] RTC_RD 2890[6] RTC_WR 2890[7] RTC_FAIL 2890[4] RTC_SBSC[7:0] 2892[7:0] 2.5.4.3 RTC Rate Control Two rate adjustment mechanisms are available: • The first rate adjustment mechanism is an analog rate ...
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... See the Real Time RTC Temperature Compensation section for details. 2.5.4.4 RTC Temperature Compensation The 71M6541D/F and 71M6542F can be configured to regularly measure die temperature, including in SLP and LCD modes and while the MPU is halted. If enabled by the OSC_COMP bit, the temperature information is automatically used to correct for the temperature variation of the crystal ...
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Referring to Figure 17, the table lookup method uses the 10-bits plus sign-bit value in STEMP[10:0] right- shifted by two bits to obtain an 8-bit plus sign value (i.e., NV RAM Address = STEMP/4). A limiter ensures that the resulting ...
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For proper operation, the MPU must load the lookup table with values that reflect the crystal properties with respect to temperature, which is typically done once during ...
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Temperature Sensor The 71M654x includes an on-chip temperature sensor for determining the temperature of its bandgap reference. The primary use of the temperature data is to determine the magnitude of compensation required to offset the thermal drift in ...
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Name Location TEMP_BAT 28A0[4] 28B4[6] TEMP_START TEMP_PWR 28A0[6] TEMP_BSEL 28A0[7] TEMP_TEST[1:0] 2500[1:0] STEMP[10:3] 2881[7:0] STEMP[2:0] 2882[7:5] BSENSE[7:0] 2885[7:0] BCURR 2704[3] Refer to the 71M6xxx Data Sheet for information on reading the temperature sensor in the 71M6x01 devices. 2.5.6 71M654x Battery ...
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... Refer to the 71M6xxx Data Sheet for information on reading the VCC sensor in the 71M6x01 devices. 2.5.7 UART and Optical Interface The 71M6541D/F and 71M6542F provide two asynchronous interfaces, UART0 and UART1. Both can be used to connect to AMR modules, user interfaces, etc., and also support a mechanism for programming the on-chip flash memory ...
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... Digital I/O and LCD Segment Drivers 2.5.8.1 General Information The 71M6541D/F and 71M6542F combine most DIO pins with LCD segment drivers. Each SEG/DIO pin can be configured as a DIO pin segment (SEG) driver pin. On reset or power-up, all DIO pins are DIO inputs (except for SEGDIO0-15, see caution note below) until they are configured as desired under MPU control. The pin function can be configured by the I/O RAM registers LCD_MAPn (0x2405 – ...
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... HIGH-Z LOW Not recommended Figure 20: Connecting an External Load to DIO Pins 60 © 2008–2011 Teridian Semiconductor Corporation Resource Selected for SEGDIOn or PB Pin Low priority I/O interrupt (INT1) (71M6541D/F) and Table 52 (71M6542F). V3P3SYS MISSION LCD/SLEEP VBAT BROWNOUT V3P3D HIGH DIO HIGH-Z LOW ...
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Digital I/O for the 71M6541D/F A total of 32 combined SEG/DIO pins plus 5 SEG outputs are available for the 71M6541D/F. These pins can be categorized as follows: 17 combined SEG/DIO segment pins: SEGDIO4…SEGDIO5 (2 pins) o SEGDIO9…SEGDIO14 (6 ...
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Table 49: Data/Direction Registers for SEGDIO19 to SEGDIO27 (71M6541D/F) SEGDIO – – Pin # – – – – Configuration DIO LCD LCD_MAP[23:19] (I/O RAM 0x2409) – – SEG Data Register – – DIO Data Register – ...
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... LCD driver by writing 1 to bit 4 of LCD_MAP[15:8]. The display information is written to bits LCD_SEG12. The configuration for pins SEGDIO16 to SEGDIO31 is shown in SEGDIO32 to SEGDIO45 is shown in pins. The configuration for pins SEGDIO51 to SEGDIO55 is shown in Table 52: Data/Direction Registers for SEGDIO0 to SEGDIO15 (71M6542F) SEGDIO 0 1 Pin # ...
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... SEG Data Register 32 33 DIO Data Register 32 33 Direction Register input output Table 55: Data/Direction Registers for SEGDIO51 to SEGDIO55 (71M6542F) SEGDIO Pin # Configuration DIO LCD SEG Data Register DIO Data Register Direction Register input output 64 © 2008–2011 Teridian Semiconductor Corporation ...
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LCD Drivers The LCD drivers are grouped into up to six commons (COM0 – COM5) and segment drivers. The LCD interface is flexible and can drive 7-segment digits, 14-segments digits or enunciator symbols. A voltage doubler ...
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The LCD system has the ability to drive up to six segments per SEG driver. If the display is configured with six back planes, the 6-way multiplexing compresses the number of SEG pins required to drive a display and therefore ...
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Table 57 shows all I/O RAM registers that control the operation of the LCD interface. Name Location Rst LCD_ALLCOM 2400[3] LCD_BAT 2402[7] LCD_E 2400[7] LCD_ON 240C[0] LCD_BLANK 240C[1] LCD_RST 240C[2] LCD_DAC[4:0] 240D[4:0] LCD_CLK[1:0] 2400[1:0] LCD_MODE[2:0] 2400[6:4] LCD_VMODE[1:0] 2401[7:6] 00 The ...
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The LCD bias may be compensated for temperature using the LCD_DAC[4:0] field (I/O RAM 0x240D[4:0]). The bias may be adjusted from 1.4 V below the 3.3 V supply (V3P3SYS in MSN mode and VBAT in BRN and LCD modes). When ...
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LCD Drivers (71M6541D/F) With a maximum of 35 LCD driver pins available, the 71M6541D/F is capable of driving 210 pixels of an LCD display when using the 6 x multiplex mode. At eight pixels ...
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... RAM fields LCD_SEG46[5:0] (I/O RAM 0x243E[5:0]) through LCD_SEG50[5:0] (I/O RAM 0x2442[5:0]); see Table 59. The associated pins function as ICE interface pins, and the ICE functionality overrides the LCD function whenever ICE_E is pulled high. Table 59: 71M6542F LCD Data Registers for SEG46 to SEG50 SEG Pin # Configuration: SEG Data Register 2 ...
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Table 60: EECTRL Bits for 2-pin Interface Status Read/ Reset Name Bit Write State 7 ERROR R 6 BUSY R 5 RX_ACK R 4 TX_ACK R 3:0 W 0000 CMD[3:0] The EEPROM interface can also be operated by controlling the ...
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Indicates that EEDATA (SFR 0x9E filled with data from EEPROM Specifies the number of clocks to be issued. Allowed values are 0 through 8. If RD=1, CNT bits of data are read MSB first, ...
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EECTRL Byte Written INT5 not issued Write -- No HiZ SCLK (output) SDATA (output) D7 SDATA output Z (LoZ) BUSY (bit) Figure 25: 3-Wire Interface. Write Command when CNT=0 EECTRL Byte Written Write -- With HiZ and WFR SCLK (output) ...
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When SPI_CSZ rises, SPI command bytes that are not of the form x000 0000 update the SPI_CMD (SFR 0xFD) register and then cause an interrupt to be issued to the MPU. The exception is if the transaction was a single ...
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SERIAL READ 16 bit Address (From Host) SPI_CSZ 0 15 (From Host) SPI_CK (From Host) SPI_DI A0 A15 A14 (From 654x) SPI_DO SERIAL WRITE 16 bit Address (From Host) SPI_CSZ 0 15 (From Host) SPI_CK A14 (From ...
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Name Location Rst 2701[7] 0 EX_SPI SPI_CMD SFR FD[7:0] – SPI_E 270C[4] 1 IE_SPI SFR F8[7] 0 270C[3] 0 SPI_SAFE 2708[7:0] 0 SPI_STAT 76 © 2008–2011 Teridian Semiconductor Corporation Table 64: SPI Registers Wk Dir Description 0 R/W SPI interrupt ...
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... In SFM mode, the MPU is completely halted. For this reason, the interrupt feature described in the SPI Transaction section above is not available in SFM mode. The 71M6541D/F and 71M6542F must be reset by the WD timer or by the RESET pin in order to exit SFM mode. ...
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... An independent, robust, fixed-duration, watchdog timer (WDT) is included in the 71M6541D/F and 71M6542F. It uses the RTC crystal oscillator as its time base and must be refreshed by the MPU firmware at least every 1.5 seconds. When not refreshed on time, the WDT overflows and the part is reset as if the ...
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The TMUXOUT and TMUX2OUT pins may be used for diagnostics purposes during the product development cycle or in the production test. The RTC 1-second output may be used to calibrate the crystal oscillator. The RTC 4-second output provides higher precision ...
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Functional Description 3.1 Theory of Operation The energy delivered by a power source into a load can be expressed as: Assuming phase angles are constant, the following formulae apply: Real Energy [Wh ...
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Battery Modes Shortly after system power (V3P3SYS) is applied, the part is in mission mode (MSN mode). MSN mode means that the part is operating with system power and that the internal PLL is stable. This mode is the ...
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... Wake-up timer timeout. • Pushbutton (PB) is activated. • A rising edge on SEGDIO4, SEGDIO52 (71M6542F only) or SEGDIO55. • Activity on the RX or OPT_RX pins. The MPU has access to a variety of registers that signal the event that caused the wake up. See Wake Up Behavior for details. ...
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BRN Mode In BRN mode, most non-metering digital functions are active (as shown in EEPROM, LCD and RTC. In BRN mode, the PLL continues to function at the same frequency as MSN mode the MPU ...
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SLP Mode When the V3P3SYS pin voltage drops below 2.8 VDC, the 71M654x enters BRN mode and the V3P3D pin obtains power from the VBAT pin instead of the V3P3SYS pin. Once in BRN mode, the MPU may invoke ...
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... SFR address 0xF9 and occupies bits [2:0], and it is read-only. In addition to the state of the main power, the VSTAT[2:0] register provides information about the internal VDD voltage under battery power. Note that if system power (V3P3A) is above 2.8 VDC, the 71M6541D/F and 71M6542F always switch from battery to system power. Description VSTAT[2:0] 000 System Power OK. V3P3A > ...
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... IC Behavior at Low Battery Voltage When system power is not present, the 71M6541D/F and 71M6542F rely on the VBAT pin for power. If the VBAT voltage is not sufficient to maintain VDD at 2.0 VDC or greater, the MPU cannot operate reliably. Low VBAT voltage can occur while the part is operating in BRN mode, or while it is dormant in SLP or LCD mode. Two cases can be distinguished, depending on MPU code: • ...
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... The following pin signal events wake the 71M654x from SLP or LCD mode: a high level on the PB pin, either edge on the RX pin, a rising edge on the SEGDIO4 pin, a high level on the SEGDIO52 pin (71M6542F only high level on the SEGDIO55 pin or either edge on the OPT_RX pin. See on each pin and for further details on the OPT_RX/SEGDIO55 pin ...
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... WF_ERST Always Enabled WF_OVF Always Enabled WF_CSTART Always Enabled WF_BADVDD † 71M6542F only. *This pin is sampled every 2 ms and must remain high for declared a valid high level. This pin is high-level sensitive. 88 © 2008–2011 Teridian Semiconductor Corporation Wake Flag De-bounce Description ...
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... R/W SEGDIO4 rising to wake the part. This bit has no effect unless SEGDIO4 is configured as a digital input. Connects DIO52 to the WAKE logic and permits DIO52 high-level to wake the part (71M6542F only). This bit – R/W has no effect unless DIO52 is configured as a digital input ...
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... Timer expiration WF_PB PB pin high level WF_RX Either edge RX pin WF_DIO4 SEGDIO4 rising edge WF_DIO52 SEGDIO52 high level (71M6542F only) If OPT_RXDIS = 1 (I/O RAM 0x2457[2]), wake on SEGDIO55 high WF_DIO55 If OPT_RXDIS = 0 wake on either edge of OPT_RX RESET pin driven high WF_RST RESET bit is set (I/O RAM 0x2200[3]) ...
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Data Flow and MPU/CE Communication The data flow between the Compute Engine (CE) and the MPU is shown in application, the 32-bit CE sequentially processes the samples from the voltage inputs on pins IA, VA, IB, etc., performing calculations ...
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Application Information 4.1 Connecting 5 V Devices All digital input pins of the 71M654x are compatible with external 5 V devices. I/O pins configured as inputs do not require current-limiting resistors when they are connected to external 5 V ...
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Using Local Sensors Figure 35 shows a 71M6541D/F configuration using locally connected current sensors. The IAP-IAN current channel may be directly connected to either a shunt resistor or a CT, while the IBP-IBN channel is connected to a ...
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Using 71M6x01and Current Shunts Figure 36 shows a typical connection for one isolated and one non-isolated shunt sensor, using the 71M6x01 Isolated Sensor Interface. This configuration implements a single-phase measurement with tamper-detection using the second current sensor. This ...
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... Using Local Sensors Figure 38 shows a 71M6542F configuration using locally connected current sensors. The IAP-IAN current channel may be directly connected to either a shunt resistor or a CT, while the IBP-IBN channel is connected and is therefore isolated. This configuration implements a dual-phase measurement utilizing Equation 2. For best performance, both the IAP-IAN and IBP-IBN current sensor inputs are configured for differential mode (i ...
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... Using 71M6x01 and Current Shunts Figure 38 shows a typical two-phase connection for the 71M6542F using one isolated and one non-isolated sensor. For best performance, the IAP-IAN current sensor input is configured for differential mode (i.e., DIFFA_E = 1, I/O RAM 0x210C[4]). The 71M6x01 Isolated Sensor Interface is used to isolate phase B. The outputs of the 71M6x01 Isolated Sensor Interface are routed through a pulse transformer, which is connected to the pins IBP-IBN ...
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Metrology Temperature Compensation 4.7.1 Voltage Reference Precision Since the VREF band-gap amplifier is chopper-stabilized, as set by the CHOP_E[1:0] (I/O RAM 0x2106[3:2]) control field, the dc offset voltage, which is the most significant long-term drift mechanism in the voltage ...
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... GAIN_ADJ0 compensates for the VA and VB (71M6542F only) voltage measurements in the 71M654x and is used to compensate the VREF in the 71M654x. The designer may optionally add compensation for the resistive voltage dividers into the PPMC and PPMC2 coefficients for this channel. • ...
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... Figure 71M6542F and is directly connected to the 71M654x. The VB voltage sensor is available only in the 71M6542F and is also directly connected to it. Thus, the precision of these directly connected voltage sensors is affected by VREF in the 71M654x. The 71M654x also has one shunt current sensor (IA) which is connected directly to it, and therefore is also affected by the VREF in the 71M654x ...
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... Teridian Semiconductor Corporation CE RAM Address 71M6541D/F 0x40 0x41 0x42 4.7.2 Temperature Coefficients for the 2 C pins SDCK and SDATA. V3P3D 10 k Ω Ω EEPROM SEGDIO2/SDCK SDCK SEGDIO3/SDATA SDATA 71M654x 2 Figure 39 EEPROM Connection 71M6542F VA VA 71M654x. For v1.1 ...
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Connecting Three-Wire EEPROMs µWire EEPROMs and other compatible devices should be connected to the DIO pins SEGDIO2/SDCK and SEGDIO3/SDATA, as described in 4.10 UART0 (TX/RX) The UART0 RX pin should be pulled down kΩ resistor and ...
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... For a production meter, the RESET pin should be protected by the external components shown in Figure 42, right side. R1 should be in the range of 100Ω and mounted as closely as possible to the IC. Since the 71M6541D/F and 71M6542F generate their own power-on reset, a reset button or circuitry, as shown in Figure 42, is only required for test units and prototypes ...
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V3P3D 62 Ω 62 Ω 62 Ω Figure 43: External Components for the Emulator Interface v1.1 © 2008–2011 Teridian Semiconductor Corporation LCD Segments (optional) 71M654x ICE_E E_RST E_RXT E_TCLK 103 ...
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... Crystal Oscillator The oscillator of the 71M6541D/F and 71M6542F drives a standard 32.768 kHz watch crystal. The oscillator has been designed specifically to handle these crystals and is compatible with their high impedance and limited power handling capability. The oscillator power dissipation is very low to maximize the lifetime of any battery backup device attached to the VBAT_RTC pin ...
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Firmware Interface 5.1 I/O RAM Map –Functional Order In Table 74 and Table 75, unimplemented (U) and reserved (R) bits are shaded in light gray. Unimplemented bits are identified with a ‘U’. Unimplemented bits have no memory storage, writing ...
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... INT2_E 2025 EX_SPI EX_WPULSE WAKE_E 2026 SFMM 2080 SFMS 2081 Notes: *SFMM and SFMS are accessible only through the SPI slave port. See Invoking SFM (page 77) for details. † 71M6542F only. 106 Bit 6 Bit 5 Bit 4 LCD_MAP[47:40] LCD_MAP[39:32] LCD_MAP[31:24] LCD_MAP[23:16] LCD_MAP[15:8] LCD_MAP[7: ...
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Table 75 lists bits and registers that may have to be accessed on a frequent basis. Reserved bits have lighter gray background, and non-volatile bits have a darker gray background. Name Addr Bit 7 CE and ADC MUX5 2100 MUX4 ...
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Name Addr Bit 7 LCD_MAP4 2407 LCD_MAP3 2408 LCD_MAP2 2409 LCD_MAP1 240A LCD_MAP0 240B LCD4 240C U LCD_DAC 240D U SEGDIO0 2410 U … … U SEGDIO15 241F U SEGDIO16 2420 U … … U SEGDIO45 243D U SEGDIO46 243E ...
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Name Addr Bit 7 TMUX2 2503 U RTC1 2504 U 71M6x01 Interface REMOTE2 2602 REMOTE1 2603 RBITS INT1_E 2700 EX_EEX EX_XPULSE INT2_E 2701 EX_SPI EX_WPULSE SECURE 2702 Analog0 2704 VREF_CAL VREF_DIS VERSION 2706 INTBITS 2707 U FLAG0 SFR E8 IE_EEX ...
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... U WDRST 28B4 WD_RST TEMP_START MPU PORTS P3 SFR B0 P2 SFR A0 P1 SFR 90 P0 SFR 80 FLASH ERASE SFR 94 FLSHCTL SFR B2 PREBOOT PGADR SFR EEDATA SFR 9E EECTRL SFR 9F † 71M6542F only 110 Bit 6 Bit 5 Bit 4 RTC_SBSC[7: RTC_YR[7: RTC_P[13:6] RTC_P[5: OSC_COMP TEMP_BAT WF_RST WF_RSTBIT ...
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I/O RAM Map – Alphabetical Order Table 76 lists I/O RAM bits and registers in alphabetical order. Bits with a write direction (W in column Dir) are written by the MPU into configuration RAM. Typically, they are initially stored ...
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Name Location 2709[7:6] CHOPR[1:0] DIFFA_E 210C[4] DIFFB_E 210C[5] DIO_R2[2:0] 2455[2:0] 2455[6:4] DIO_R3[2:0] DIO_R4[2:0] 2454[2:0] DIO_R5[2:0] 2454[6:4] 2453[2:0] DIO_R6[2:0] DIO_R7[2:0] 2453[6:4] DIO_R8[2:0] 2452[2:0] 2452[6:4] DIO_R9[2:0] DIO_R10[2:0] 2451[2:0] 2451[6:4] DIO_R11[2:0] 2450[2:0] DIO_RPB[2:0] DIO_DIR[15:12] SFR B0[7:4] DIO_DIR[11:8] SFR A0[7:4] DIO_DIR[7:4] SFR 90[7:4] SFR ...
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... VA*(IA-IB)/ element, 3W 1φ VA*IA + VB*IB † element, 3W 3φ Delta Note: 1. Optionally, IB may be used to measure neutral current. † 71M6542F only © 2008–2011 Teridian Semiconductor Corporation Reset Polarity Description State 1 when an illegal command 0 Positive is received. 0 Positive 1 when serial data bus is busy ...
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... This bit has no effect unless SEGDIO52 is configured as a – 0 R/W digital input. The SEGDIO52 pin is only available in the 71M6542F. Connects SEGDIO55 to the WAKE logic and permits SEGDIO55 rising to – 0 R/W wake the part. This bit has no effect unless SEGDIO55 is configured as a digital input ...
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Name Location SFR 94[7:0] FLSH_ERASE[7:0] FLSH_MEEN SFR B2[1] FLSH_PEND SFR B2[3] FLSH_PGADR[5:0] SFR B7[7:2] FLSH_PSTWR SFR B2[2] FLSH_PWE SFR B2[0] FLSH_RDE 2702[2] FLSH_UNLOCK[3:0] 2702[7:4] FLSH_WRE 2702[1] v1.1 Rst Wk Dir Description Flash Erase Initiate FLSH_ERASE is used to initiate either ...
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Name Location IE_XFER SFR E8[0] IE_RTC1S SFR E8[1] SFR E8[2] IE_RTC1M IE_RTCT SFR E8[4] IE_SPI SFR F8[7] IE_EEX SFR E8[7] IE_XPULSE SFR E8[6] IE_YPULSE SFR E8[5] SFR F8[4] IE_WPULSE IE_VPULSE SFR F8[3] INTBITS 2707[6:0] LCD_ALLCOM 2400[3] LCD_BAT 2402[7] LCD_BLNKMAP23[5:0] 2401[5:0] ...
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... SEG and DIO data for SEGDIO51 through SEGDIO55. If configured as DIO, bit 1 is direction (1 is output input), bit 0 is data, and the other bits are 0 – R/W ignored. SEGDIO52 through SEDIO54 are available only on the 71M6542F. © 2008–2011 Teridian Semiconductor Corporation LCD_MODE Output 100 Static display ...
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Name Location 2401[7:6] LCD_VMODE[1:0] LCD_Y 2400[2] LKPADDR[6:0] 2887[6:0] LKPAUTOI 2887[7] LKPDAT[7:0] 2888[7:0] LKP_RD 2889[1] LKP_WR 2889[0] 2200[2:0] MPU_DIV[2:0] MUX0_SEL[3:0] 2105[3:0] MUX1_SEL[3:0] 2105[7:4] MUX2_SEL[3:0] 2104[3:0] MUX3_SEL[3:0] 2104[7:4] MUX4_SEL[3:0] 2103[3:0] MUX5_SEL[3:0] 2103[7:4] MUX6_SEL[3:0] 2102[3:0] MUX7_SEL[3:0] 2102[7:4] MUX8_SEL[3:0] 2101[3:0] MUX9_SEL[3:0] 2101[7:4] MUX10_SEL[3:0] 2100[3:0] ...
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Name Location MUX_DIV[3:0] 2100[7:4] OPT_BB 2457[0] 2457[5:4] OPT_FDC[1:0] OPT_RXDIS 2457[2] OPT_RXINV 2457[1] OPT_TXE [1:0] 2456[3:2] OPT_TXINV 2456[0] OPT_TXMOD 2456[1] OSC_COMP 28A0[5] SFR F8[0] PB_STATE PERR_RD SFR FC[6] PERR_WR SFR FC[5] PLL_OK SFR F9[4] v1.1 Rst Wk Dir Description MUX_DIV[3:0] is ...
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Name Location PLL_FAST 2200[4] PLS_MAXWIDTH[7:0] 210A[7:0] PLS_INTERVAL[7:0] 210B[7:0] PLS_INV 210C[0] PORT_E 270C[5] 2704[5] PRE_E PREBOOT SFRB2[7] RCMD[4:0] SFR FC[4:0] RESET 2200[3] 210C[3] RFLY_DIS 120 Rst Wk Dir Description Controls the speed of the PLL and MCK R/W 1 ...
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Name Location 2709[3] RMT_E 2602[7:0] RMT_RD[15:8] RMT_RD[7:0] 2603[7:0] RTC_FAIL 2890[4] RTC_P[16:14] 289B[2:0] RTC_P[13:6] 289C[7:0] 289D[7:2] RTC_P[5:0] RTC_Q[1:0] 289D[1:0] 2890[6] RTC_RD RTC_SBSC[7:0] 2892[7:0] RTC_TMIN[5:0] 289E[5:0] 289F[4:0] RTC_THR[4:0] RTC_WR 2890[7] RTC_SEC[5:0] 2893[5:0] RTC_MIN[5:0] 2894[5:0] RTC_HR[4:0] 2895[4:0] 2896[2:0] RTC_DAY[2:0] RTC_DATE[4:0] 2897[4:0] RTC_MO[3:0] 2898[3:0] ...
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Name Location RTM_E 2106[1] RTM0[9:8] 210D[1:0] RTM0[7:0] 210E[7:0] RTM1[7:0] 210F[7:0] RTM2[7:0] 2110[7:0] RTM3[7:0] 2111[7:0] SFR B2[6] SECURE SLEEP 28B2[7] SPI_CMD[7:0] SFR FD[7:0] SPI_E 270C[4] SPI_SAFE 270C[3] 2708[7:0] SPI_STAT[7:0] STEMP[10:3] 2881[7:0] STEMP[2:0] 2882[7:5] SUM_SAMPS[12:8] 2107[4:0] SUM_SAMPS[7:0] 2108[7:0] TBYTE_BUSY 28A0[3] 122 Rst ...
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Name Location TEMP_22[10:8] 230A[2:0] TEMP_22[7:0] 230B[7:0] TEMP_BAT 28A0[4] TEMP_BSEL 28A0[7] TBYTE_BUSY 28A0[3] 28A0[2:0] TEMP_PER[2:0] 28A0[6] TEMP_PWR TEMP_START 28B4[6] TMUX[5:0] 2502[5:0] 2503[4:0] TMUX2[4:0] TMUXRA[2:0] 270A[2:0] VERSION[7:0] 2706[7:0] VREF_CAL 2704[7] 2704[6] VREF_DIS v1.1 Rst Wk Dir Description 0 – R Storage location ...
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Name Location VSTAT[2:0] SFR F9[2:0] WAKE_ARM 28B2[5] WAKE_TMR[7:0] 2880[7:0] 28B4[7] WD_RST WF_DIO4 28B1[2] WF_DIO52 28B1[1] WF_DIO55 28B1[0] WF_TMR 28B1[5] WF_PB 28B1[3] WF_RX 28B1[4] WF_CSTART 28B0[7] WF_RST 28B0[6] WF_RSTBIT 28B0[5] WF_OVF 28B0[4] WF_ERST 28B0[3] WF_BADVDD 28B0[2] 124 Rst Wk Dir Description ...
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... Please contact the local Teridian representative to obtain the appropriate CE code required for a specific application. Device 71M6541D/F 71M6542F 5.3.2 CE Data Format All CE words are 4 bytes. Unless specified otherwise, they are in 32-bit two’s complement format (-1 = 0xFFFFFFFF). Calibration parameters are defined in flash memory (or external EEPROM) and must be copied to CE data memory by the MPU before enabling the CE ...
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... VA IA – 1 element, 2W 1φ 1 VA*(IA-IB)/2 – 1 element, 3W 1φ † 2 VA*IA + VB*IB – 2 element, 3W 3φ Delta Note: † 71M6542F only. 126 © 2008–2011 Teridian Semiconductor Corporation 5.2 I/O RAM Map – Alphabetical Order Table 1 and Table 2. Figure 6 ...
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... VA Notes: * Remote interface data. † 71M6542F only. 5.3.7 FCE Status and Control The CE Status Word, CESTATUS, is useful for generating early warnings to the MPU sag warnings for phase A and B, as well as F0, the derived clock operating at the fundamental input fre- quency. The MPU can read the CE status word at every CE_BUSY interrupt. Since the CE_BUSY inter- rupt occurs at 2520 ...
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... CE Name Address 0x0030DB00 0x20 CECONFIG 0x00B0DB00 1. Default for CE41A01 (71M6541D/F or CE41A04 (71M6542F) CE code for use with local sensors. 2. Default for CE41B016201 and CE41B016601 codes that support the 71M6x01 remote sensors. Table 83: CECONFIG (CE RAM 0x20) Bit Definitions CECONFIG Name Default Description ...
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... SAG_THR (CE RAM 0x24) register and the SAG_CNT field in CECONFIG (CE RAM 0x20[19:8]). When the SAG_INT bit (CE RAM 0x20[20]) is set sag event generates a transition on the YPULSE output two-phase system (71M6542F), and after a sag interrupt, the MPU should change the FREQSEL[1:0] setting to select the other phase powered. Even though a sag interrupt is only generated on the selected phase, both phases are simultaneously checked for sag ...
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When the MPU receives the XFER_BUSY interrupt, it knows that fresh data is available in the transfer variables. CE transfer variables are modified during the CE code pass that ends with an XFER_BUSY interrupt. They remain constant throughout each accumulation ...
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Instantaneous Energy Measurement Variables IxSQSUM_X and VxSQSUM (see acquired during the last accumulation interval. Table 87: CE Energy Measurement Variables (with Local Sensors) CE Name Address The sum of squared current samples from each 0x8C I0SQSUM_X element. 0x8D I1SQSUM_X ...
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CE Name Address 0x82 FREQ_X 0x83 MAINEDGE_X 5.3.9 Pulse Generation Table 90 describes the CE pulse generation parameters. The combination of the CECONFIG PULSE_SLOW and PULSE_FAST bits (CE RAM 0x20[0:1]) controls the speed of the pulse rate. The default values ...
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CE Name Default Address 0x21 WRATE 0x22 KVAR 6444 0x23 SUM_SAMPS 2520 0x45 APULSEW 0x46 WPULSE_CTR 0x47 WPULSE_FRAC WSUM_ACCUM 0x48 0x49 APULSER 0x4A VPULSE_CTR 0x4B VPULSE_FRAC 0x4C VSUM_ACCUM v1.1 © 2008–2011 Teridian Semiconductor Corporation Description VMAX = Kh WRATE where: ...
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Other CE Parameters Table 91 shows the CE parameters used for suppression of noise due to scaling and truncation effects. Table 91: CE Parameters for Noise Suppression and Code Version CE Name Default Address 0x25 QUANT_VA 0x26 QUANT_IA 0x27 ...
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CE Calibration Parameters Table 92 lists the parameters that are typically entered to effect calibration of meter accuracy. CE Name Default Address 0x10 CAL_IA 16384 0x11 CAL_VA 16384 0x13 16384 CAL_IB † 0x14 16384 CAL_VB 0x12 0 PHADJ_A 0x15 ...
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CE Flow Diagrams Figure 44 through Figure 46 show the data flow through the CE in simplified form. Functions not shown include delay compensation, sag detection, scaling and the processing of meter equations. Figure 44: CE Data Flow: Multiplexer ...
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W0 W1 VAR0 VAR1 SQUARE Figure 46: CE Data Flow: Squaring and Summation Stages v1.1 © 2008–2011 Teridian Semiconductor Corporation SUM Σ Σ Σ Σ SUM_SAMPS=2520 SUM I0SQ Σ V0SQ Σ 2 I1SQ ...
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... Solder temperature – 10 second duration ESD stress on all pins 138 © 2008–2011 Teridian Semiconductor Corporation Table 93: Absolute Maximum Ratings Voltage and Current † † ( 71M6542F only) Temperature and ESD Stress 6.3 −0 4 4 +0 +10 mA, -0 V3P3A+0 mA, -0 ...
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Recommended External Components Table 94: Recommended External Components Name From To C1 V3P3A GNDA C2 V3P3D GNDD CSYS V3P3SYS GNDD CVDD VDD GNDD CVLCD VLCD GNDD XTAL XIN XOUT CXS XIN GNDA CXL XOUT GNDA 6.3 Recommended Operating Conditions ...
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Performance Specifications 6.4.1 Input Logic Levels Parameter 1 Digital high-level input voltage 1 Digital low-level input voltage , V Input pullup current E_RXTX, E_RST, E_TCLK OPT_RX, OPT_TX SPI_CSZ (SEGDIO36) Other digital inputs Input pull down current, I ...
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Battery Monitor Table 98: Battery Monitor Performance Specifications (TEMP_BAT= 1) Parameter BV: Battery Voltage (definition) Measurement Error BV ⋅ − 100 1 VBAT Input impedance in continuous measurement, MSN mode. V(VBAT_RTC)/I(VBAT_RTC) Load applied ...
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Supply Current The supply currents provided in Refer to the 71M6xxx Data Sheet for additional current required when using a 71M6x01 remote sensor. Table 100: Supply Current Performance Specifications Parameter I1: V3P3A + V3P3SYS current, Half-Speed (ADC_DIV=1) (see note ...
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V3P3D Switch Table 101: V3P3D Switch Performance Specifications Parameter On resistance – V3P3SYS to V3P3D On resistance – VBAT to V3P3D V3P3D I , MSN OH V3P3D I , BRN OH 6.4.7 Internal Power Fault Comparators Table 102. Internal ...
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V Voltage Regulator – Battery Power Unless otherwise specified, V3P3SYS = V3P3A = 0, PB=GND (BRN). Table 104: Low-Power Voltage Regulator Performance Specifications Parameter V2P5 V2P5 load regulation Voltage Overhead 2V − VBAT-VDD 6.4.10 Crystal Oscillator Measurement conditions: ...
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LCD Drivers Table 107: LCD Driver Performance Specifications PARAMETER VLCD=3.3, all LCD map bits=0 VLCD Current VLCD=5.0, all LCD map bits=0 Note: 1. These specifications apply to all COM and SEG pins. 2. VLCD = 2 ...
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VLCD Generator Table 108: LCD Driver Performance Specifications Parameter VSYS to VLCD switch impedance VBAT to VLCD switch impedance LCD Boost Frequency VLCD IOH current (VLCD(0)-VLCD(IOH)<0.25) ������������ ( ������_������ 5���� �������������0 + From LCDADJ0 and LCDADJ12 fuses: ...
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Parameter LCD_DAC Error. VLCD-VLCDnom DAC=12, no Boost V3P3 = 3.6 V V3P3 = 3.0 V VBAT = 4.0 V, V3P3 = 0 V, BRN Mode VBAT = 2.5 V, V3P3 = 0 V, BRN Mode LCD_DAC Error. VLCD-VLCDnom Zero Scale, ...
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VREF Table 109 shows the performance specifications for the ADC reference voltage (VREF). Table 109: VREF Performance Specifications Parameter VREF output voltage, VREF(22) VREF output voltage, VREF(22) VREF output impedance VREF power supply sensitivity ΔVREF / ΔV3P3A VREF input ...
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... v1.1 © 2008–2011 Teridian Semiconductor Corporation Condition Vin = 200 mV peak, 65 Hz, on VADC10 (VA VADC9 (VB)† †71M6542F only. Vcrosstalk = largest measurement on IAP-IAN or IBP-IBN Vin=65 Hz Vin=200 mV pk V3P3A=3.0 V, 3.6 V DIFF0_E=1, PRE_E=0 DIFF0_E=0, PRE_E 65Hz, 250mVpk, IN 64kpts FFT, Blackman Harris 3 Window 65Hz, 20mVpk, IN 64kpts FFT, Blackman Harris 3 Window ...
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Note: 1. Guaranteed by design; not production tested. 2. Unless stated otherwise, the following test conditions apply to all the parameters provided in this table: FIR_LEN[1:0]=1, VREF_DIS=0, PLL_FAST=1, ADC_DIV=0, MUX_DIV=6, LSB values do not include the 9-bit left shift at ...
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Timing Specifications 6.5.1 Flash Memory Table 112: Flash Memory Timing Specifications Parameter Flash write cycles Flash data retention Flash byte writes between page or mass erase operations Write Time per Byte Page Erase (1024 bytes) Mass Erase 6.5.2 SPI ...
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RTC Parameter Range for date 152 © 2008–2011 Teridian Semiconductor Corporation Table 116: RTC Range for Date Condition Min Typ Max Unit 2000 - 2255 year v1.1 ...
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Package Outline Drawings 6.6.1 64-Pin LQFP Outline Package Drawing 11.7 12.3 PIN No. 1 Indicator 0.60 Typ. Figure 47: 64-pin LQFP Package Outline v1.1 © 2008–2011 Teridian Semiconductor Corporation 11.7 12.3 9.8 10.2 0.14 0.50 Typ. 0.28 0.00 0.20 ...
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LQFP Package Outline Drawing Controlling dimensions are in mm. 1 14.000 +/- 0.200 0.225 +/- 0.045 Figure 48: 100-pin LQFP Package Outline 154 © 2008–2011 Teridian Semiconductor Corporation 15.7(0.618) 16.3(0.641) Top View MAX. 1.600 1.50 +/- 0.10 0.50 ...
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Pinout Diagrams 6.7.1 71M6541D/F LQFP-64 Package Pinout SPI_DI/SEGDIO38 1 SPI_DO/SEGDIO37 2 SPI_CSZ/SEGDIO36 3 4 COM0 5 COM1 COM2 6 COM3 7 8 SEGDIO27/COM4 9 SEGDIO26/COM5 10 SEGDIO25 11 SEGDIO24 12 SEGDIO23 SEGDIO22 13 SEGDIO21 14 15 SEGDIO20 16 SEGDIO19 ...
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... SEGDIO29 10 SEGDIO28 11 COM0 12 COM1 13 COM2 14 COM3 15 SEGDIO27/COM4 16 SEGDIO26/COM5 17 SEGDIO25 18 SEGDIO24 19 SEGDIO23 20 SEGDIO22 21 SEGDIO21 22 SEGDIO20 23 SEGDIO19 24 SEGDIO18 25 Figure 50: Pinout for the 71M6542F (LQFP-100 Package) 156 © 2008–2011 Teridian Semiconductor Corporation Teridian 71M6542F XIN GNDA 72 VBAT_RTC 71 VBAT 70 V3P3SYS 69 IBP 68 67 IBN GNDD ...
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Pin Descriptions 6.8.1 Power and Ground Pins Pin types Power Output Input, I/O = Input/Output. The circuit number denotes the equivalent circuit, as specified under . Pin Pin Name (64 pin) (100-pin) 50 ...
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... XIN 49 76 XOUT † Pin VB only available on 71M6542F. 158 © 2008–2011 Teridian Semiconductor Corporation Table 118: Analog Pins Differential or single-ended Line Current Sense Inputs: These pins are voltage inputs to the internal A/D converter. Typically, they are connected to the outputs of current sensors ...
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Digital Pins Table 119 lists the digital pins. Pin types Power Output Input, I/O = Input/Output, N connect. The circuit number denotes the equivalent circuit, as specified in Pin Pin Name ...
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Pin Pin Name (64-pin) (100-pin ICE_E 60 92 TMUXOUT/SEG47 61 93 TMUX2OUT/SEG46 59 91 RESET TEST 26, 40, 48, 49, 50, 63, 64, 65 66, ...
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I/O Equivalent Circuits V3P3D V3P3D 110K Digital CMOS Input Input Pin GNDD Digital Input Equivalent Circuit Type 1: Standard Digital Input or pin configured as DIO Input with Internal Pull-Up V3P3D Digital CMOS Input Input Pin 110K GNDD GNDD ...
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... KB bulk 71M6541F-IGT/F tape and 64 KB 71M6541F-IGTR/F 71M6541F-IGT reel 128 KB bulk 71M6541G-IGT/F tape and 128 KB 71M6541G-IGTR/F 71M6541G-IGT reel 64 KB bulk 71M6542F-IGT/F tape and 64 KB 71M6542F-IGTR/F 71M6542F-IGT reel 128 KB bulk 71M6542G-IGT/F tape and 128 KB 71M6542G-IGTR/F 71M6542G-IGT reel Package Marking 71M6541D-IGT 71M6541F-IGT ...
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Appendix A: Acronyms AFE Analog Front End AMR Automatic Meter Reading ANSI American National Standards Institute CE Compute Engine DIO Digital I /O DSP Digital Signal Processor FIR Finite Impulse Response Inter-IC Bus ICE In-Circuit Emulator IEC ...
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Appendix B: Revision History REVISION REVISION NUMBER DATE 1.0 3/11 Initial release Removed the information about 18mW typ consumption at 3.3V in sleep mode from the Features section 1.1 4/11 Updated the Temperature Measurement Equation and Temperature Error parameters in ...
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... Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time 2011 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products. ...