71M6543F-IGTR/F Maxim Integrated Products, 71M6543F-IGTR/F Datasheet - Page 44
![no-image](/images/manufacturer_photos/0/4/417/maxim_integrated_products_sml.jpg)
71M6543F-IGTR/F
Manufacturer Part Number
71M6543F-IGTR/F
Description
PMIC Solutions Precision Energy Meter IC
Manufacturer
Maxim Integrated Products
Type
Metering SoCr
Datasheet
1.71M6543F-DB.pdf
(157 pages)
Specifications of 71M6543F-IGTR/F
Core
8051
Core Architecture
8051
Data Bus Width
8 bit
Data Ram Size
5 KB
Device Million Instructions Per Second
5 MIPS
Interface Type
I2C, ICE, SPI, UART
Maximum Clock Frequency
5 MHz
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Number Of Programmable I/os
51
Number Of Timers
2
On-chip Adc
22 bit
Operating Supply Voltage
3 V to 3.6 V
Package / Case
LQFP-100
Processor Series
8051
Program Memory Size
64 KB
Program Memory Type
Flash
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
71M6543F-IGTR/F
Manufacturer:
Maxim Integrated
Quantity:
10 000
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71M6543F/H and 71M6543G/GH Data Sheet
IP1(SFR 0xB9)
polling sequence as shown in
44
Register
IP0
IP1
Changing interrupt priorities while interrupts are enabled can easily cause software defects. It is best
to set the interrupt priority registers only once during initialization before interrupts are enabled.
SFR 0xA9
SFR 0xB9
(Table
Address
36). If requests of the same priority level are received simultaneously, an internal
Table 36: Interrupt Priority Registers (IP0 and IP1)
© 2008–2011 Teridian Semiconductor Corporation
(MSB)
Bit 7
Table 37
–
–
IP1[x]
0
0
1
1
Table 35: Interrupt Priority Levels
Bit 6
determines which request is serviced first.
–
–
IP0[x]
0
1
0
1
IP0[5]
IP1[5]
Bit 5
Level 0 (lowest)
Level 1
Level 2
Level 3 (highest)
IP0[4]
IP1[4]
Bit 4
Priority Level
IP0[3]
IP1[3]
Bit 3
IP0[2]
IP1[2]
Bit 2
IP0[1]
IP1[1]
Bit 1
IP0[0]
IP1[0]
(LSB)
Bit 0
v1.2
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