CAT813TZI-GT3 Catalyst / ON Semiconductor, CAT813TZI-GT3 Datasheet - Page 7

Supervisory Circuits 4.65V Active-High

CAT813TZI-GT3

Manufacturer Part Number
CAT813TZI-GT3
Description
Supervisory Circuits 4.65V Active-High
Manufacturer
Catalyst / ON Semiconductor
Datasheet

Specifications of CAT813TZI-GT3

Number Of Voltages Monitored
1
Monitored Voltage
3 V, 3.6 V, 5 V
Manual Reset
Resettable
Watchdog
Watchdog
Supply Voltage (max)
5.5 V
Supply Voltage (min)
1.2 V
Supply Current (typ)
17 uA
Maximum Power Dissipation
330 mW
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Package / Case
MSOP-8
Minimum Operating Temperature
- 40 C
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
FUNCTIONAL DESCRIPTION
PROCESSOR RESET
The CAT705, CAT706 & CAT813 detect supply
voltage (V
voltage trip value (V
maintain correct system operation. On power-up,
¯¯¯¯¯¯ (or RESET for the CAT813) are kept active for
RESET
a minimum delay t
(V
processor to stabilize. When V
voltage trip value (V
¯¯¯¯¯¯ (or RESET) are pulled active.
RESET
RESET) is specifically designed to provide the reset
input signals for processors. This provides reliable
and consistent operation as power is turned on, off or
during brownout conditions by maintaining the
processor operation in known conditions.
© 2010 SCILLC. All rights reserved.
Characteristics subject to change without notice
CC
) rises above V
CC
) conditions that are below the specified
RP
RESET
RESET
MR
RST
RST
of 140ms after the supply voltage
RST
) and provide a reset output to
to allow the power supply and
), the reset output signals
Figure 2. Timing Diagram – Pushbutton RESET
V
CC
IL
t
PDLY
drops below the
Figure 1. Pushbutton RESET
RESET
¯¯¯¯¯¯ (or
t
PB
GND
V
MR
PFI
CC
CAT705
CAT706
CAT813
7
MANUAL RESET
The CAT705, CAT706 & CAT813 each have a Manual
Reset (MR
reset outputs. The MR
connection to a pushbutton (see Figure 1). The MR
input is internally pulled up by 52kΩ resistor and must
be pulled low to cause the reset output to go active.
Internally, this input is debounced and timed such that
¯¯¯¯¯¯ (or RESET) signals of at least 140ms
RESET
minimum will be generated. The min 140ms t
commences as the Manual Reset input is released
from the low level. (see Figure 2)
V
WDO
RESET/RESET
WDI
PFO
IH
t
RP
¯¯¯ ) input to allow for alternative control of the
V
V
OH
OL
¯¯¯ input is designed for direct
CAT705, CAT706, CAT813
Doc. No. MD-3030, Rev. E
RP
delay
¯¯¯

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