DP83848CVVX/NOPB National Semiconductor, DP83848CVVX/NOPB Datasheet - Page 45

• Manufacturer Part Number: DP83848CVVX/NOPB
• Description: TXRX ETHERNET PHYTER 48-LQFP
• Manufacturer: National Semiconductor
• Type: Transceiverr

Specifications of DP83848CVVX/NOPB

• Number Of Drivers/receivers: 1/1
• Protocol: Ethernet
• Voltage - Supply: 3 V ~ 3.6 V
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP
• For Use With: DP83848C-POE-EK - BOARD EVALUATION DP83848CDP83848C-MAU-EK - BOARD EVALUATION DP83848C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: DP83848CVVX

The PHY Identifier Registers #1 and #2 together form a unique identifier for the DP83848C. The Identifier consists of a
concatenation of the Organizationally Unique Identifier (OUI), the vendor's model number and the model revision num-
ber. A PHY may return a value of zero in each of the 32 bits of the PHY Identifier if desired. The PHY Identifier is intended
to support network management. National's IEEE assigned OUI is 080017h.
7.1.3 PHY Identifier Register #1 (PHYIDR1)
7.1.4 PHY Identifier Register #2 (PHYIDR2)
7.1.5 Auto-Negotiation Advertisement Register (ANAR)
This register contains the advertised abilities of this device as they will be transmitted to its link partner during Auto-Nego-
tiation.
15:10
15:0
Bit
Bit
9:4
3:0
Bit
15
14
13
12
VNDR_MDL
RESERVED
RESERVED
MDL_REV
OUI_MSB
Bit Name
Bit Name
Bit Name
OUI_LSB
NP
RF
Table 16. Negotiation Advertisement Register (ANAR), address 0x04
Table 14. PHY Identifier Register #1 (PHYIDR1), address 0x02
Table 15. PHY Identifier Register #2 (PHYIDR2), address 0x03
<0010 0000 0000
0000>, RO/P
<0101 11>, RO/P OUI Least Significant Bits:
<00 1001>, RO/P Vendor Model Number:
<0000>, RO/P
0, RO/P
Default
Default
Default
0, RW
0, RW
0, RW
OUI Most Significant Bits: Bits 3 to 18 of the OUI (080017h) are
stored in bits 15 to 0 of this register. The most significant two bits
of the OUI are ignored (the IEEE standard refers to these as bits 1
and 2).
Bits 19 to 24 of the OUI (080017h) are mapped from bits 15 to 10
of this register respectively.
The six bits of vendor model number are mapped from bits 9 to 4
(most significant bit to bit 9).
Model Revision Number:
Four bits of the vendor model revision number are mapped from
bits 3 to 0 (most significant bit to bit 3). This field will be incremented
for all major device changes.
Next Page Indication:
0 = Next Page Transfer not desired.
1 = Next Page Transfer desired.
RESERVED by IEEE: Writes ignored, Read as 0.
Remote Fault:
1 = Advertises that this device has detected a Remote Fault.
0 = No Remote Fault detected.
RESERVED for Future IEEE use: Write as 0, Read as 0
45
Description
Description
Description
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