DS90CF383BMT/NOPB National Semiconductor, DS90CF383BMT/NOPB Datasheet

IC FPD-LINK 24BIT TX 56-TSSOP

DS90CF383BMT/NOPB

Manufacturer Part Number
DS90CF383BMT/NOPB
Description
IC FPD-LINK 24BIT TX 56-TSSOP
Manufacturer
National Semiconductor
Type
Transmitterr
Datasheet

Specifications of DS90CF383BMT/NOPB

Number Of Drivers/receivers
4/0
Protocol
RS644
Voltage - Supply
3 V ~ 3.6 V
Mounting Type
Surface Mount
Package / Case
56-TSSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
DS90CF383BMT

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DS90CF383BMT/NOPB
Manufacturer:
TI
Quantity:
1 000
© 2006 National Semiconductor Corporation
DS90CF383B
+3.3V Programmable LVDS Transmitter 24-Bit Flat Panel
Display (FPD) Link-65 MHz
General Description
The DS90CF383B transmitter converts 28 bits of CMOS/TTL
data into four LVDS (Low Voltage Differential Signaling) data
streams. A phase-locked transmit clock is transmitted in
parallel with the data streams over a fifth LVDS link. Every
cycle of the transmit clock 28 bits of input data are sampled
and transmitted. At a transmit clock frequency of 65 MHz, 24
bits of RGB data and 3 bits of LCD timing and control data
(FPLINE, FPFRAME, DRDY) are transmitted at a rate of 455
Mbps per LVDS data channel. Using a 65 MHz clock, the
data throughput is 227 Mbytes/sec. The DS90CF383B is
fixed as a Falling edge strobe transmitter and will interoper-
ate with a Falling edge strobe Receiver (DS90CF386) with-
out any translation logic.
This chipset is an ideal means to solve EMI and cable size
problems associated with wide, high speed TTL interfaces.
Features
n No special start-up sequence required between
n Support Spread Spectrum Clocking up to 100KHz
Block Diagram
TRI-STATE
clock/data and /PD pins. Input signal (clock and data)
can be applied either before or after the device is
powered.
frequency modulation & deviations of
spread or −5% down spread.
®
is a registered trademark of National Semiconductor Corporation.
DS200985
±
2.5% center
See NS Package Number MTD56
Order Number DS90CF383BMT
DS90CF383B
n "Input Clock Detection" feature will pull all LVDS pairs to
n 18 to 68 MHz shift clock support
n Best–in–Class Set & Hold Times on TxINPUTs
n Tx power consumption
n 40% Less Power Dissipation than BiCMOS Alternatives
n Tx Power-down mode
n Supports VGA, SVGA, XGA and Dual Pixel SXGA.
n Narrow bus reduces cable size and cost
n Up to 1.8 Gbps throughput
n Up to 227 Megabytes/sec bandwidth
n 345 mV (typ) swing LVDS devices for low EMI
n PLL requires no external components
n Compatible with TIA/EIA-644 LVDS standard
n Low profile 56-lead TSSOP package
n Improved replacement for:
logic low when input clock is missing and when /PD pin
is logic high.
Grayscale
SN75LVDS83, DS90CF383A
<
<
60µW (typ)
20098501
130 mW (typ)
@
65MHz
October 2005
www.national.com

Related parts for DS90CF383BMT/NOPB

DS90CF383BMT/NOPB Summary of contents

Page 1

... Block Diagram TRI-STATE ® registered trademark of National Semiconductor Corporation. © 2006 National Semiconductor Corporation n "Input Clock Detection" feature will pull all LVDS pairs to logic low when input clock is missing and when /PD pin is logic high. ...

Page 2

... Absolute Maximum Ratings If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage ( CMOS/TTL Input Voltage LVDS Driver Output Voltage LVDS Output Short Circuit Duration Junction Temperature Storage Temperature Lead Temperature (Soldering, 4 sec) ...

Page 3

Electrical Characteristics Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter TRANSMITTER SUPPLY CURRENT ICCTG Transmitter Supply Current 16 Grayscale ICCTZ Transmitter Supply Current Power Down Note 1: “Absolute Maximum Ratings” are those values beyond which the ...

Page 4

Transmitter Switching Characteristics Over recommended operating supply and temperature ranges unless otherwise specified Symbol TPPos0 Transmitter Output Pulse Position for Bit 0 (Figure 11 ) (Note 5) TPPos1 Transmitter Output Pulse Position for Bit 1 TPPos2 Transmitter Output Pulse Position ...

Page 5

AC Timing Diagrams (Continued) FIGURE 2. “16 Grayscale” Test Pattern (Notes 10) Note 7: The worst case test pattern produces a maximum toggling of digital circuits, LVDS I/O and CMOS/TTL I/O. Note 8: The 16 grayscale test ...

Page 6

AC Timing Diagrams FIGURE 5. DS90CF383B (Transmitter) Input Clock Transition Time FIGURE 6. DS90CF383B (Transmitter) Setup/Hold and High/Low Times (Falling Edge Strobe) FIGURE 7. DS90CF383B (Transmitter) Clock In to Clock Out Delay (Falling Edge Strobe) FIGURE 8. DS90CF383B (Transmitter) Phase ...

Page 7

AC Timing Diagrams (Continued) FIGURE 9. 28 Parallel TTL Data Inputs Mapped to LVDS Outputs FIGURE 10. Transmitter Power Down Delay 7 20098517 20098518 www.national.com ...

Page 8

AC Timing Diagrams FIGURE 11. Transmitter LVDS Output Pulse Position Measurement www.national.com (Continued) 8 20098526 ...

Page 9

DS90CF383B Pin Descriptions — FPD Link Transmitter Pin Name I/O No. TxIN I 28 TTL level input. This includes: 8 Red, 8 Green, 8 Blue, and 4 control lines — FPLINE, FPFRAME and DRDY (also referred to as HSYNC, VSYNC, ...

Page 10

Pin Diagram www.national.com DS90CF383B 20098524 Typical Application 10 20098503 ...

Page 11

... BANNED SUBSTANCE COMPLIANCE National Semiconductor follows the provisions of the Product Stewardship Guide for Customers (CSP-9-111C2) and Banned Substances and Materials of Interest Specification (CSP-9-111S2) for regulatory environmental compliance. Details may be found at: www.national.com/quality/green. ...

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