PEF82912FV14XP Lantiq, PEF82912FV14XP Datasheet - Page 176

• Manufacturer Part Number: PEF82912FV14XP
• Manufacturer: Lantiq

Specifications of PEF82912FV14XP

• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / Rohs Status: Supplier Unconfirmed

4.8.3
MODE1
Value after reset: 04
MCLK
CDS
WTC1, 2
Data Sheet
7
MODE1 - Mode1 Register
Master Clock Frequency
The Master Clock Frequency bits control the microcontroller clock output
depending on MODE1.CDS = ’0’ or ’1’ (Table
00 =
01 =
10 =
11 =
Clock Divider Selection
0 =
1 =
Watchdog Timer Control 1, 2
After the watchdog timer mode has been selected (RSS = ‘11’) the
watchdog timer is started. During every time period of 128 ms the
microcontroller has to program the WTC1 and WTC2 bit in the following
sequence
10
01
to reset and restart the watchdog timer.
If not, the timer expires and a WOV-interrupt (ISTA Register) together with
a reset out pulse on pin RSTO is generated.
The watchdog timer runs only when the internal IOM
i.e. the watchdog timer is dead when bit CFS = 1 and the U and S-
transceivers are in state power down.
MCLK
MODE1.CDS = ’0’
3.84 MHz
0.96 MHz
7.68 MHz
disabled
The 15.36 MHz oscillator clock divided by two is input to the MCLK
prescaler
The 15.36 MHz oscillator clock is input to the MCLK prescaler.
first step
second step
H
(Chapter
CDS
2.2):
WTC1
read/write
162
MODE1.CDS = ’1’
7.68 MHz
1.92 MHz
15.36 MHz
disabled
WTC2
Table
CFS
2.1.3).
®
Register Description
-2 clocks are active,
PEF 82912/82913
RSS2
Address:
2001-03-30
RSS1
0
3D
H