PEF82912FV14XP Lantiq, PEF82912FV14XP Datasheet - Page 192

• Manufacturer Part Number: PEF82912FV14XP
• Manufacturer: Lantiq

Specifications of PEF82912FV14XP

• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / Rohs Status: Supplier Unconfirmed

MRE
MRC
MIE
MXC
4.10.5
MSTA
Value after reset: 00
Data Sheet
7
0
MSTA - MONITOR Status Register
MONITOR Receive Interrupt Enable
0 =
1 =
MR Bit Control
Determines the value of the MR bit:
0 =
1 =
MONITOR Interrupt Enable
0 =
1 =
MX Bit Control
Determines the value of the MX bit:
0 =
1 =
0
MONITOR interrupt status MDR generation is masked.
MONITOR interrupt status MDR generation is enabled.
MR is always ‘1’. In addition, the MDR interrupt is blocked, except
for the first byte of a packet (if MRE = 1).
MR is internally controlled by the Q-SMINT I according to
MONITOR channel protocol. In addition, the MDR interrupt is
enabled for all received bytes according to the MONITOR channel
protocol (if MRE = 1).
MONITOR interrupt status MER, MDA, MAB generation is masked
MONITOR interrupt status MER, MDA, MAB generation is enabled
The MX bit is always ‘1’.
The MX bit is internally controlled by the Q-SMINT I according to
MONITOR channel protocol.
H
0
0
read
178
0
MAC
Register Description
PEF 82912/82913
Address:
0
2001-03-30
TOUT
0
5F
H