PSB3186HV14XP Lantiq, PSB3186HV14XP Datasheet - Page 45
PSB3186HV14XP
Manufacturer Part Number
PSB3186HV14XP
Description
Manufacturer
Lantiq
Datasheet
1.PSB3186HV14XP.pdf
(200 pages)
Specifications of PSB3186HV14XP
Number Of Line Interfaces
1
Control Interface
HDLC
Lead Free Status / Rohs Status
Compliant
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Figure 19
3.3.4
The full-bauded pseudo-ternary pulse shaping is achieved with the integrated transmitter
which is realized as a symmetrical current limited voltage source (V
I
The nominal pulse amplitude on the S-interface 750 mV (zero-peak) is adjusted with
external resistors (see
Data Sheet
max
NT -> TE
TE -> NT
FSC
DU
DD
Mapping of a 4-bit group of D-bits on S and IOM depends on prehistory (e.g. priority control):
= 26 mA). The equivalent circuit of the transmitter is shown in
B1
B1
Transmitter Characteristics
F
B2 D
B2 D
F
Data Delay between IOM-2 and S/T Interface with S/G Bit Evaluation
B1
B1
E
Mapping of B-Channel Timeslots
1. Possibility
2. Possibility
D
D
Chapter
B2
E
B2
E
B1
B1
B2 D
B2 D
D
D
3.3.6.1).
B1
B1
E
D
D
B2
B2
E
E
45
B1
B1
D
F
D
B2 D
F
B2 D
B1
B1
E
Description of Functional Blocks
D
D
B2
E
B2
E
B1
B1
B2 D
B2 D
D
D
B1
Figure
B1
E
SX1/SX2
D
ISAC-SX TE
D
20.
B2
line_iom_s_dch.vsd
PSB 3186
B2
E
E
= +/-1.0 V;
2003-01-30
D
D
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