PEB24911HV13 Lantiq, PEB24911HV13 Datasheet - Page 118

• Manufacturer Part Number: PEB24911HV13
• Manufacturer: Lantiq

Specifications of PEB24911HV13

• Lead Free Status / Rohs Status: Supplier Unconfirmed

Boundary Scan
Number
TDI ––>
TAP Controller
The Test Access Port (TAP) controller implements the state machine defined in the
JTAG standard IEEE 1149.1. Transitions on pin TMS cause the TAP controller to
perform a state change. Before operation the TAP controller has to be reset by TRST.
According to the IEEE 1149 standard 7 instructions are executable. The instructions
’CLAMP’ and ’HIGHZ’ were added. Instructions ’SSP’ and ’DT’ are no more supported
since its function is identical to that of the SSP and DT pins.
•
Table 14
0000
0001
0010
0011
0100
0101
1111
EXTEST is used to examine the board interconnections.
When the TAP controller is in the state "update DR", all output pins are updated with the
falling edge of TCK. When it has entered state "capture DR" the levels of all input pins
are latched with the rising edge of TCK. The in/out shifting of the scan vectors is typically
done using the instruction SAMPLE/PRELOAD.
INTEST supports internal chip testing.
When the TAP controller is in the state "update DR", all inputs are updated internally with
the falling edge of TCK. When it has entered state "capture DR" the levels of all outputs
Data Sheet
46.
47.
48.
49.
50.
Code
Instruction
EXTEST
INTEST
SAMPLE/PRELOAD
IDCODE
CLAMP
HIGHZ
BYPASS
TAP Controller Instructions:
Pin Number
10
8
7
5
4
Pin Name
Function
External testing
Internal testing
Snap-shot testing
Reading ID code
Reading outputs
Z-State of all boundary scan output pins
Bypass operation
PDM1
PDM2
PDM3
CL15
SDR
108
Type
I
I
I
I
I
Operational Description
Number of
Scan Cells
PEF 24911
2001-07-16
1
1
1
1
1