MC145574AAER2 Freescale Semiconductor, MC145574AAER2 Datasheet - Page 126

• Manufacturer Part Number: MC145574AAER2
• Manufacturer: Freescale Semiconductor

Specifications of MC145574AAER2

• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / Rohs Status: Compliant

18–4
18.5.2
IDL2 Slave Timing, 8- and 10-Bit Formats
NOTES:
Ref. No.
1. FSC occurs on average every 125 s. FSC must occur every 125 s with a maximum instantaneous phase titter of 30 s.
2. In IDL2 8– and 10–bit formats, TSEN is valid during the B1, B2, and D channel timeslots. TSEN will be aligned with data
3. In IDL2 Slave mode, DCL may be any frequency multiple of 8 kHz between 256 kHz and 4.096 MHz inclusive.
14
15
16
17
18
19
20
21
22
23
24
25
26
on the D out pin.
FSC Period
FSC High Before the Falling Edge of DCL (FSC Setup Time)
FSC High After the Falling Edge of DCL (FSC Hold Time)
Delay From Rising Edge of DCL to Low–Z and Valid Data on
D out
Delay From Rising Edge of DCL to Data Valid on D out
Delay From Rising Edge of DCL to High–Z on D out
Delay From Rising Edge of DCL to TSEN Low
Delay From Rising Edge of DCL to TSEN High
DCL Clock Period
DCL Pulse Width High
DCL Pulse Width Low
Data Valid on D in Before Falling Edge of DCL (D in Setup Time)
Data Valid on D in After Falling Edge of DCL (D in Hold Time)
Freescale Semiconductor, Inc.
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Parameter
MC145574
Min
125
244
25
25
—
—
—
—
45
45
25
25
5
1953
Max
30
30
30
30
30
55
55
—
—
—
—
—
% of DCL
% of DCL
MOTOROLA
Period
Period
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
s
Note
1
2
3