MC145574AAER2 Freescale Semiconductor, MC145574AAER2 Datasheet - Page 96

• Manufacturer Part Number: MC145574AAER2
• Manufacturer: Freescale Semiconductor

Specifications of MC145574AAER2

• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / Rohs Status: Compliant

10–6
10.10
enabled, dual frame syncs cannot be enabled. TSEN D channel signal can be enabled only if TSEN
B1/B2 channel signals are enabled (OR7(1) = 1).
OR8
OR8(7) — Reserved
This bit is reserved.
OR8(6) — Reserved
This bit is reserved.
OR8(5) — Disable XTAL
When an external 15.36 MHz is provided, this bit can be set to 1 to disable the internal crystal buffer,
thereby reducing unnecessary power consumption.
OR8(4) — Control Register, TE Mode Enable
When the device is initialized, this bit is a logic 0. When set to a logic 0, the device operates as normal
in all modes. This bit is OR’d with the TE/NT pin and TE mode can be selected by setting this bit
to a 1.
OR8(3) — Control Register, Master Mode Enable
When the device is initialized, this bit is a logic 0. When set to a logic 0, the device operates as normal
in all modes. This bit is OR’d with the M/S pin and the NT master bit, BR7(3), and master mode can
be selected by setting this bit to a 1.
OR8(2) — Control Register, FIX Enable
When the device is initialized, this bit is a logic 0. When set to a logic 0, the device operates as normal
in all modes. In all NT modes except NT Terminal, the FIX register bit is OR’d with the FIX pin. In
NT Terminal mode, the FIX bit completely replaces the function of the FIX pin. Fixed timing mode
can be selected in NT mode by setting this bit to a 1.
OR8(1) — Control Register, NT Terminal Mode Enable
When the device is initialized, this bit is a logic 0. When set to a logic 0, the device operates as normal
in all modes. NT Terminal mode can be enabled by setting this bit to 1. This bit only functions when
the device is in NT mode. NT Terminal mode allows the device to have a D channel terminal port
enabled. Refer to the section on NT Terminal mode.
OR8(0) — Control Register, Sleep Enable
When the device is initialized, this bit is a logic 0. When set to a logic 0, the device operates as normal
in all modes. Please refer to the section on power modes for further operational details.
OR8
Reserved
(7)
Freescale Semiconductor, Inc.
For More Information On This Product,
Reserved
(6)
Go to: www.freescale.com
Disable
MC145574
XTAL
(5)
TE Mode
Enable
(4)
Master
Enable
Mode
(3)
FIX Enable
(2)
Terminal
Enable
Mode
NT
(1)
MOTOROLA
Enable
Sleep
(0)