A3PE-BRD600-SKT MICROSEMI, A3PE-BRD600-SKT Datasheet - Page 16

• Manufacturer Part Number: A3PE-BRD600-SKT
• Description: MCU, MPU & DSP Development Tools ProASIC3/E Starter Kit
• Manufacturer: MICROSEMI

Specifications of A3PE-BRD600-SKT

• Processor To Be Evaluated: ProASIC3/E
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Hardware Components
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The momentary push button switches (SW5 and SW6, for applying a reset pulse and a global pulse) are connected via
jumpers JP15 and JP16 to I/Os 159 and 113 respectively. Again, all labeling is clearly shown on the silk screen.
The hex switches U13 and U14 each are connected to four I/Os on the FPGA. There are four separate jumpers for each
of these hex switches, located on the bottom right of the board. They are labeled with Bit0, Bit1, Bit2, and Bit3 on the
silk screen, as well as being labeled with the I/O pin on the FPGA to which each is connected. This allows you to
individually control the desired effect of a switch and, by connecting directly to the FPGA side of a disconnected jumper,
hold a particular pin at a chosen logic level while continuing to use the hex switch to affect other pins. This flexibility is
useful for experimentation with designs of your own choosing and connecting other external equipment to the board for
development purposes.
The internal and external oscillator selection via JP24 is worth a mention. JP24 is a three-pin header onto which a
normal two-hole shunt is fitted. Normally the shunt is connected across pins 3 and 2 of JP24. In this position the on-
board oscillator, U1, provides the internal clock to the middle pin of the jumper which in turn is connected to pin 26 of
the FPGA. By moving the shunt down to connect pins 2 and 1 of JP24, the external clock at pin 1 is connected to the
FPGA instead. The external clock is connected via the SMA connector J19 at the bottom left of the board.
The LCD display also has associated jumpers for the data: JP41, JP42, JP43, and JP44, located on the top left side of the
board. These are connected to I/O pins 197, 198, 194, and 193 respectively. The LCD control signals “Enable,” “R/W,”
and “RS” are provided from I/O pins 190, 192, and 191 via jumpers JP47, JP45, and JP46 respectively.
Test Points
All test points on the board are fitted with small test loops. These test points are labeled on the silkscreen as TP1, TP2,
etc. All such test points are also labeled on the silk screen with the voltage expected to be observed at that test point.
Voltages will be one of 3.3 V, 2.5 V, 1.8 V, 1.5 V or GND. When measuring the voltage at a test point with a DVM
(digital voltage multimeter), the ground lead should be connected to a test point labeled GND and the voltage lead
should be connected to the voltage to be tested. All voltage labels on the board are relative to a 0 V ground reference or
GND.
Prototyping Area
The prototyping area to the right of the board has the bottom two rows of pins connected to ground, labeled as GND on
the silk screen and enclosed in a box, giving 16 holes connected to 0 V. The top two rows of pins are connected to various
power supply rails internally in the board. They are grouped into squares of four pins from left to right as follows: 3.3 V,
2.5 V, 1.8 V, and 1.5 V, giving four holes for each voltage level. All other holes in the prototyping area are unconnected
and may be used to hold various discrete components as necessary for experimentation.
Next to the prototyping area is U2, which is a space for an optional oscillator. This space may be used for fitting a second
oscillator to the board, similar to the one used at U1, so as to provide two different frequency clocks to the FPGA.
On the reverse side of the board, there is an area labeled U5, which is a TQ100 pattern with some surrounding pads.
This area may be used to solder a TQ100 part, and then connect that part by adding discrete wires to the pads and
connecting it to desired pins on the board. The main purpose of this is to allow a previously programmed TQ100
packaged device to be used to provide a more interesting system application.
Layering on Board
The complete board design and manufacturing files are included on the Starter Kit CD. The board file is in Allegro
format, which will allow an end user to create the appropriate Gerbers and other board views as needed. Pictures of the
layers of the board are also attached in
these layers are also provided on the Starter Kit CD.
Appendix C
of this User’s Guide. For your convenience, high-resolution PDFs of
ProASIC3/E Starter Kit User’s Guide and Tutorial