K4S641632N-LC75000 Samsung Semiconductor, K4S641632N-LC75000 Datasheet - Page 12

• Manufacturer Part Number: K4S641632N-LC75000
• Manufacturer: Samsung Semiconductor
• Type: SDRAMr

Specifications of K4S641632N-LC75000

• Organization: 4Mx16
• Density: 64Mb
• Address Bus: 14b
• Access Time (max): 6/4.5ns
• Maximum Clock Rate: 133MHz
• Operating Supply Voltage (typ): 3.3V
• Package Type: TSOP-II
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Supply Current: 110mA
• Pin Count: 54
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / Rohs Status: Compliant

Notes :
14.0 AC Characteristics
15.0 DQ Buffer Output Drive Characteristics
Notes :
CLK cycle time
CLK to valid
output delay
Output data
hold time
CLK high pulse width
CLK low pulse width
Input setup time
Input hold time
CLK to output in Low-Z
CLK to output
in Hi-Z
K4S640832N
K4S641632N
Output rise time
Output fall time
Output rise time
Output fall time
Parameter
1. Parameters depend on programmed CAS latency.
2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter.
3. Assumed input rise and fall time (tr & tf) = 1ns.
4. t
1. Rise time specification based on 0pF + 50 Ω to V
2. Fall time specification based on 0pF + 50 Ω to V
3. Measured into 50pF only, use these values to characterize to.
4. All measurements done with respect to V
If tr & tf is longer than 1ns, transient time compensation should be considered,
i.e., [(tr + tf)/2-1]ns should be added to the parameter.
t
SS
SH
applies for address setup time
applies for address holde time, clock enable hold time, commend hold time and data hold time
Parameter
CAS latency=3
CAS latency=2
CAS latency=3
CAS latency=2
CAS latency=3
CAS latency=2
CAS latency=3
CAS latency=2
Symbol
trh
tfh
trh
tfh
Symbol
Measure in linear
region : 1.2V ~ 1.8V
Measure in linear
region : 1.2V ~ 1.8V
Measure in linear
region : 1.2V ~ 1.8V
Measure in linear
region : 1.2V ~ 1.8V
,
tSAC
tSHZ
clock enable setup time
tSLZ
tOH
tCC
tCH
tSH
tCL
tSS
Condition
SS
.
Min
1.5
50 (x16 only)
5
2
2
2
1
1
-
-
-
-
-
-
DD
SS
, use these values to design to.
, use these values to design to.
12 of 15
1000
Max
4.5
4.5
,
-
-
-
-
-
-
-
-
-
commend setup time and data setup time
1.37
1.30
Min
2.8
2.0
Min
2.5
2.5
2.5
1.5
10
60 (x16 only)
6
3
1
1
-
-
-
-
Typ
3.9
2.9
(AC operating conditions unless otherwise noted)
1000
Max
5
6
5
6
-
-
-
-
-
-
-
Synchronous DRAM
Rev. 1.12 August 2008
Max
4.37
3.8
5.6
5.0
Min
7.5
2.5
2.5
1.5
0.8
10
3
3
1
-
-
-
-
75
Volts/ns
Volts/ns
Volts/ns
Volts/ns
1000
Max
Unit
5.4
5.4
6
6
-
-
-
-
-
-
-
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
1,2
1,2
3
3
Note
3, 4
3, 4
1,2
1
2
3
3
2