ADNS-3050 Avago Technologies US Inc., ADNS-3050 Datasheet - Page 9

• Manufacturer Part Number: ADNS-3050
• Description: Optical Sensors - Board Mount Optical Nav Sensor
• Manufacturer: Avago Technologies US Inc.

Specifications of ADNS-3050

• Lead Free Status / Rohs Status: Details

Table 3. AC Electrical Specifi cations
Electrical characteristics over recommended operating conditions. Typical values at 25 °C, VDD = 2.8 V.
9
Parameter
Motion Delay after Reset
Power Down
Wake from Power Down
MISO Rise Time
MISO Fall Time
MISO Delay after SCLK
MISO Hold Time
MOSI Hold Time
MOSI Setup Time
SPI Time between
Write Commands
SPI Time between
Write and Read Command
SPI Time between Read and
Subsequent Commands
SPI Read Address-Data Delay t
NCS to SCLK Active
SCLK to NCS Inactive
(for Read Operation)
SCLK to NCS Inactive
(for Write Operation)
NCS to MISO high-Z
Transient Supply Current
Symbol
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
I
DDT
MOT-RST
PD
WAKEUP
r-MISO
f-MISO
DLY-MISO
hold-MISO
hold-MOSI
setup-MOSI
SWW
SWR
SRW
SRR
SRAD
NCS-SCLK
SCLK-NCS
SCLK-NCS
NCS-MISO
Min.
50
500
200
120
30
20
250
4
120
120
20
Typ.
40
40
Max.
50
50
55
200
200
120
1/fSCLK
250
60
Units
ms
ms
ms
ns
ns
ns
ns
ns
ns
μs
μs
ns
μs
ns
ns
μs
ns
mA
Notes
From RESET register write to valid motion
From PD active to low current (when bit 1
of register 0x0d is set)
From PD inactive to valid motion (when
write 0x5a to register 0x3a)
CL = 100 pF
CL = 100 pF
From SCLK falling edge to MISO data valid,
no load condition
Data held until next falling SCLK edge
Amount of time data is valid after SCLK
rising edge
From data valid to SCLK rising edge
From rising SCLK for last bit of the first data
byte, Commands to rising SCLK for last bit
of the second data byte
From rising SCLK f or last bit of the first
data byte, to rising SCLK for last bit of the
second address byte
From rising SCLK for last bit of the first data
byte, to falling SCLK for the first bit of the
next address
From rising SCLK for last bit of the address
byte, to falling SCLK for first bit of data
being read
From NCS falling edge to first SCLK falling
edge
From last SCLK rising edge to NCS rising
edge, for valid MISO data transfer
From last SCLK rising edge to NCS rising
edge, for valid MOSI data transfer
From NCS rising edge to MISO high-Z state
Max supply current during a VDD ramp
from 0 to VDD