LM3481QMM/NOPB National Semiconductor, LM3481QMM/NOPB Datasheet - Page 10

• Manufacturer Part Number: LM3481QMM/NOPB
• Description: Low Side NFET Controller
• Manufacturer: National Semiconductor
• Series: -r

Specifications of LM3481QMM/NOPB

• Pwm Type: Current Mode
• Number Of Outputs: 1
• Frequency - Max: 1MHz
• Duty Cycle: 85%
• Voltage - Supply: 2.97 V ~ 48 V
• Buck: No
• Boost: Yes
• Flyback: Yes
• Inverting: No
• Doubler: No
• Divider: No
• Cuk: No
• Isolated: No
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 10-TFSOP, 10-MSOP (0.118", 3.00mm Width)
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

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To prevent the sub-harmonic oscillations, a compensation
ramp is added to the control signal, as shown in
With the compensation ramp, ΔV
criteria are expressed by,
The compensation ramp has been added internally in the
LM3481. The slope of this compensation ramp has been se-
lected to satisfy most applications, and it's value depends on
the switching frequency. This slope can be calculated using
the formula:
In the above equation, V
compensation ramp and f
quency. Limits for V
characteristics section.
In order to provide the user additional flexibility, a patented
scheme has been implemented inside the IC to increase the
SL
have been specified in the electrical
M
C
SL
S
= V
is the controller's switching fre-
is the amplitude of the internal
FIGURE 3. Compensation Ramp Avoids Sub-Harmonic Oscillation
SL
x f
samp1
S
and the convergence
FIGURE 2. Sub-Harmonic Oscillation for D>0.5
Figure
3.
10
slope of the compensation ramp externally, if the need arises.
Adding a single external resistor, R
increases the amplitude of the compensation ramp as shown
in
FIGURE 4. Additional Slope Compensation Added Using
Where,
K = 40 µA typically and changes slightly as the switching fre-
quency changes.
on ΔV
changes.
Figure
SL
and different values of R
4.
Figure 6
External Resistor R
ΔV
SL
shows the effect the current K has
= K x R
SL
as the switching frequency
20136511
SL
SL
(as shown in
20136509
SL
201365a1
Figure
5)