MM912H634CM1AER2 Freescale Semiconductor, MM912H634CM1AER2 Datasheet - Page 118
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MM912H634CM1AER2
Manufacturer Part Number
MM912H634CM1AER2
Description
64KS12 LIN2xLS/HS Isense
Manufacturer
Freescale Semiconductor
Series
-r
Datasheet
1.MM912G634CM1AE.pdf
(345 pages)
Specifications of MM912H634CM1AER2
Applications
Automotive
Core Processor
HCS12
Program Memory Type
FLASH (64 kB)
Controller Series
HCS12
Ram Size
6K x 8
Interface
LIN
Number Of I /o
-
Voltage - Supply
5.5 V ~ 27 V
Operating Temperature
-40°C ~ 125°C
Mounting Type
Surface Mount
Package / Case
48-LQFP Exposed Pad
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
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4.18.4
4.18.4.1
4.18.4.2
Freescale Semiconductor
Note:
Note:
103.
104.
Offset
Offset
Reset
DDRB[2-0]
Reset
PUEB[2-0]
W
W
R
R
Field
6-4
2-0
(103)
(104)
Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.
Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.
0x20
0x21
Register definition
Port B Configuration Register 1 (PTBC1)
Pull-up Enable Port B[2…0]
Data Direction Port B[2…0]
Port B Configuration Register 2 (PTBC2)
7
0
0
7
0
0
The pull-up resistor is not active once the port is configured as an output.
0 - Pull-up disabled on PTBx pin.
1- Pull-up enabled on PTBx pin.
0 - PTBx configured as input.
1 - PTBx configured as output.
PUEB2
6
0
0
6
0
Table 157. Port B Configuration Register 2 (PTBC2)
Table 155. Port B Configuration Register 1 (PTBC1)
Table 156. PTBC1 - Register Field Descriptions
PUEB1
MM912_634 Advance Information, Rev. 4.0
5
0
0
5
0
PUEB0
NOTE
4
0
0
4
0
Description
PWMCS
3
0
3
0
0
PWMEN
DDRB2
2
0
2
0
General Purpose I/O - PTB[0…2]
DDRB1
1
0
Access: User read/write
1
0
Access: User read/write
SERMOD
DDRB0
0
0
0
0
118
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