STK16C68-W25I Cypress Semiconductor Corp, STK16C68-W25I Datasheet - Page 8
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STK16C68-W25I
Manufacturer Part Number
STK16C68-W25I
Description
Manufacturer
Cypress Semiconductor Corp
Type
NVSRAMr
Datasheet
1.STK16C68-W25I.pdf
(10 pages)
Specifications of STK16C68-W25I
Word Size
8b
Organization
8Kx8
Density
64Kb
Interface Type
Parallel
Access Time (max)
25ns
Operating Supply Voltage (typ)
5V
Package Type
PDIP
Operating Temperature Classification
Industrial
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
4.5V
Operating Temp Range
-40C to 85C
Pin Count
28
Mounting
Through Hole
Supply Current
90mA
Lead Free Status / Rohs Status
Not Compliant
March 2006
STK16C68
The software sequence must be clocked with E
controlled
Once the sixth address in the sequence has been
entered, the
chip will be disabled. It is important that
cycles and not
sequence, although it is not necessary that G be
low for the sequence to be valid. After the t
cycle time has been fulfilled, the
activated for
SOFTWARE NONVOLATILE RECALL
A software
sequence of
to the software
RECALL
operations must be performed:
Internally,
the
1. Read address
2. Read address
3. Read address
4. Read address
5. Read address
6. Read address
1. Read address
2. Read address
3. Read address
4. Read address
5. Read address
6. Read address
SRAM
100
80
60
40
20
0
cycle, the following sequence of
data is cleared, and second, the nonvola-
READ
RECALL
Figure 2: I
READ
STORE
READ
RECALL
s.
50
STORE
WRITE
and
is a two-step procedure. First,
operations in a manner similar
0000 (hex)
1555 (hex)
0AAA (hex)
1FFF (hex)
10F0 (hex)
0F0F (hex)
0000 (hex)
1555 (hex)
0AAA (hex)
1FFF (hex)
10F0 (hex)
0F0E (hex)
cycle will commence and the
CC
Cycle Time (ns)
WRITE
cycle is initiated with a
100
(max) Reads
initiation. To initiate the
cycles be used in the
operation.
150
SRAM
Valid READ
Valid READ
Valid READ
Valid READ
Valid READ
Initiate STORE cycle
Valid READ
Valid READ
Valid READ
Valid READ
Valid READ
Initiate RECALL cycle
TTL
CMOS
200
will again be
READ
READ
STORE
8
tile information is transferred into the
After the t
be ready for
RECALL
Nonvolatile Elements. The nonvolatile data can be
recalled an unlimited number of times.
HARDWARE PROTECT
The STK16C68 offers hardware protection against
inadvertent
during low-voltage conditions. When V
software
inhibited.
LOW AVERAGE ACTIVE POWER
The STK16C68 draws significantly less current
when it is cycled at times longer than 50ns. Figure 2
shows the relationship between I
time. Worst-case current consumption is shown for
both
perature range, V
chip enable). Figure 3 shows the same relationship
for
less than 100%, only standby current is drawn
when the chip is disabled. The overall average cur-
rent drawn by the STK16C68 depends on the fol-
lowing items: 1)
duty cycle of chip enable; 3) the overall cycle rate
for accesses; 4) the ratio of
the operating temperature; 6) the V
O loading.
WRITE
Document Control # ML0010 rev 0.2
CMOS
100
80
60
40
20
0
operation in no way alters the data in the
STORE
RECALL
cycles. If the chip enable duty cycle is
and
STORE
Figure 3: I
READ
cycle time the
TTL
operations and
CMOS
50
CC
operation and
input levels (commercial tem-
= 5.5V, 100% duty cycle on
and
Cycle Time (ns)
CC
vs.
100
(max) Writes
WRITE
TTL
READ
SRAM
150
input levels; 2) the
CC
SRAM WRITE
TTL
CMOS
operations. The
CC
s to
and
will once again
SRAM WRITE
level; and 7) I/
200
CC
SRAM
READ
WRITE
< V
SWITCH
s are
cells.
cycle
s; 5)
s
,