DS21348G Maxim Integrated Products, DS21348G Datasheet - Page 31

• Manufacturer Part Number: DS21348G
• Description: IC LIU T1/E1/J1 3.3V 49-BGA
• Manufacturer: Maxim Integrated Products
• Type: Line Interface Units (LIUs)r

Specifications of DS21348G

• Number Of Drivers/receivers: 1/1
• Protocol: T1/E1/J1
• Voltage - Supply: 3.135 V ~ 3.465 V
• Mounting Type: Surface Mount
• Package / Case: 49-CSBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

CCR3 (02H): COMMON CONTROL REGISTER 3
SYMBOL
TPRBSE
(MSB)
TUA1
ATUA1
LIRST
TAOZ
TUA1
TLCE
IBPV
IBE
ATUA1
POSITION
CCR3.7
CCR3.6
CCR3.5
CCR3.4
CCR3.3
CCR3.2
CCR3.1
CCR3.0
TAOZ
DESCRIPTION
Transmit Unframed All Ones. The polarity of this bit is set such that the
device will transmit an all ones pattern on power-up or device reset. This
bit must be set to a one to allow the device to transmit data. The
transmission of this data pattern is always timed off of the JACLK (See
Figure
0 = transmit all ones at TTIP and TRING
1 = transmit data normally
Automatic Transmit Unframed All Ones. Automatically transmit an
unframed all ones pattern at TTIP and TRING during a receive carrier loss
(RCL) condition or receive all ones condition.
0 = disabled
1 = enabled
Transmit Alternate Ones and Zeros. Transmit a …101010… pattern at
TTIP and TRING. The transmission of this data pattern is always timed
off of TCLK
0 = disabled
1 = enabled
Transmit PRBS Enable. Transmit a 2
TTIP and TRING
0 = disabled
1 = enabled
Transmit Loop Code Enable. Enables the transmit side to transmit the
loop up code in the Transmit Code Definition registers (TCD1 and
TCD2). See Section
0 = disabled
1 = enabled
Line Interface Reset. Setting this bit from a zero to a one will initiate an
internal reset that resets the clock recovery state machine and re-centers
the jitter attenuator. Normally this bit is only toggled on power-up. Must
be cleared and set again for a subsequent reset.
Insert BPV. A 0 to 1 transition on this bit will cause a single BiPolar
Violation (BPV) to be inserted into the transmit data stream. Once this bit
has been toggled from a 0 to a 1, the device waits for the next occurrence
of three consecutive ones to insert the BPV. This bit must be cleared and
set again for a subsequent error to be inserted
Insert Bit Error. A 0 to 1 transition on this bit will cause a single logic
error to be inserted into the transmit data stream. This bit must be cleared
and set again for a subsequent error to be inserted
1-1).
TPRBSE
(Figure
(Figure
31 of 76
4
1-1).
and
TLCE
1-3).
Figure 1-3
for details.
LIRST
15
- 1 (E1) or a 2
(Figure
(Figure
IBPV
1-3).
20
- 1 (T1) PRBS at
1-3).
(LSB)
IBE