DS21Q48 Maxim Integrated Products, DS21Q48 Datasheet - Page 33

IC LIU E1/T1/J1 QUAD 5V 144-BGA

DS21Q48

Manufacturer Part Number
DS21Q48
Description
IC LIU E1/T1/J1 QUAD 5V 144-BGA
Manufacturer
Maxim Integrated Products
Type
Line Interface Units (LIUs)r
Datasheets

Specifications of DS21Q48

Protocol
E1
Voltage - Supply
4.75 V ~ 5.25 V
Mounting Type
Surface Mount
Package / Case
144-CSBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Drivers/receivers
-

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Table 4-5. Internal Rx Termination Select
CCR6 (05H): COMMON CONTROL REGISTER 6
(CCR5.1)
SYMBOL
(MSB)
ARLBE
LLB
RT1
ALB
LLB
RLB
0
0
1
1
(CCR5.0)
RLB
POSITION
RT0
CCR6.7
CCR6.6
CCR6.5
CCR6.4
0
1
0
1
ARLBE
Internal receive-side termination disabled
Internal receive-side 120Ω enabled
Internal receive-side 100Ω enabled
Internal receive-side 75Ω enabled
DESCRIPTION
Local Loopback. In Local Loopback (LLB), transmit data will be
looped back to the receive path passing through the jitter attenuator if it
is enabled. Data in the transmit path will act as normal. See
and Section
0 = loopback disabled
1 = loopback enabled
Remote Loopback. In Remote Loopback (RLB), data output from the
clock/data recovery circuitry will be looped back to the transmit path
passing through the jitter attenuator if it is enabled. Data in the receive
path will act as normal while data presented at TPOS and TNEG will be
ignored. See
0 = loopback disabled
1 = loopback enabled
Automatic Remote Loopback Enable and Reset. When this bit is set
high, the device will automatically go into remote loopback when it
detects loop-up code programmed into the receive loop-up code
definition registers (RUPCD1 and RUPCD2) for a minimum of 5
seconds and it will also set the RIR2.1 status bit. Once in a RLB state, it
will remain in this state until it has detected the loop code programmed
into the receive loop-down code definition registers (RDNCD1 and
RDNCD2) for a minimum of 5 seconds at which point it will force the
device out of RLB and clear RIR2.1. Toggling this bit from a 1 to a 0
can reset the automatic RLB circuitry. The action of the automatic
remote loopback circuitry is logically ORed with the RLB (CCR6.6)
control bit (i.e., either one can cause a RLB to occur).
Analog Loopback. In analog loopback (ALB), signals at TTIP and
TRING will be internally connected to RTIP and RRING. The incoming
signals, from the line, at RTIP and RRING will be ignored. The signals
at TTIP and TRING will be transmitted as normal. See
Section
0 = loopback disabled
1 = loopback enabled
TERMINATION CONFIGURATION
6.2.3
INTERNAL RECEIVE
ALB
6.2.2
Figure 1-1
for more details.
33 of 73
for details.
RJAB
and Section
ECRS2
6.2.1
for details.
ECRS1
Figure 1-1
Figure 1-1
ECRS0
(LSB)
and

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