DS26528GN+ Maxim Integrated Products, DS26528GN+ Datasheet - Page 116
![IC TXRX T1/E1/J1 OCT 256-CSBGA](/photos/6/50/65053/256-csbga_21-0315_sml.jpg)
DS26528GN+
Manufacturer Part Number
DS26528GN+
Description
IC TXRX T1/E1/J1 OCT 256-CSBGA
Manufacturer
Maxim Integrated Products
Type
Transceiverr
Datasheet
1.DS26528G.pdf
(276 pages)
Specifications of DS26528GN+
Number Of Drivers/receivers
4/4
Protocol
IEEE 1149.1
Voltage - Supply
3.135 V ~ 3.465 V
Mounting Type
Surface Mount
Package / Case
256-CSBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 7: Channel 8 Framer and BERT Software Reset (FSRST8). Framer logic and registers are reset with a 0-to-1
transition in this bit. The reset is released when a zero is written to this bit.
Bit 6: Channel 7 Framer and BERT Software Reset (FSRST7). Framer logic and registers are reset with a 0-to-1
transition in this bit. The reset is released when a zero is written to this bit.
Bit 5: Channel 6 Framer and BERT Software Reset (FSRST6). Framer logic and registers are reset with a 0-to-1
transition in this bit. The reset is released when a zero is written to this bit.
Bit 4: Channel 5 Framer and BERT Software Reset (FSRST5). Framer logic and registers are reset with a 0-to-1
transition in this bit. The reset is released when a zero is written to this bit.
Bit 3: Channel 4 Framer and BERT Software Reset (FSRST4). Framer logic and registers are reset with a 0-to-1
transition in this bit. The reset is released when a zero is written to this bit.
Bit 2: Channel 3 Framer and BERT Software Reset (FSRST3). Framer logic and registers are reset with a 0-to-1
transition in this bit. The reset is released when a zero is written to this bit.
Bit 1: Channel 2 Framer and BERT Software Reset (FSRST2). Framer logic and registers are reset with a 0-to-1
transition in this bit. The reset is released when a zero is written to this bit.
Bit 0: Channel 1 Framer and BERT Software Reset (FSRST1). Framer logic and registers are reset with a 0-to-1
transition in this bit. The reset is released when a zero is written to this bit.
0 = Normal operation
1 = Reset framer and BERT
0 = Normal operation
1 = Reset framer and BERT
0 = Normal operation
1 = Reset framer and BERT
0 = Normal operation
1 = Reset framer and BERT
0 = Normal operation
1 = Reset framer and BERT
0 = Normal operation
1 = Reset framer and BERT
0 = Normal operation
1 = Reset framer and BERT
0 = Normal operation
1 = Reset framer and BERT
FSRST8
7
0
FSRST7
GFSRR
Global Framer and BERT Software Reset Register
0F6h
6
0
FSRST6
5
0
FSRST5
116 of 276
4
0
FSRST4
3
0
DS26528 Octal T1/E1/J1 Transceiver
FSRST3
2
0
FSRST2
1
0
FSRST1
0
0
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