VRS51C1000-40-LG Ramtron, VRS51C1000-40-LG Datasheet

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... Versa 8051 MCU with 64KB of IAP/ISP Flash Overview The VRS51C1000 is based on the standard 8051 microcontroller family architecture and is pin compatible and a drop-in replacement for most 8051 MCUs. The VRS51C1000 is ideal for a range of applications requiring a large amount of program/data memory with non-volatile data storage and/or code/field based firmware upgrade capability comprehensive peripheral support ...

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... PWM Channel 0 P1.3 I/O Bit 3 of Port 1 PWM1 O PWM Channel 1 P1.4 I/O Bit 4 of Port PWM2/P1 P0.4/AD4 PWM3/P1.6 P0.5/AD5 8 38 PWM4/P1.7 9 P0.6/AD6 37 RES P0.7/AD7 36 10 VRS51C1000 35 RXD/P3.0 11 #EA P4.3 PLCC-44 34 P4.1 12 TXD/P3 ALE 32 #INT0/P3.2 14 #PSEN #INT1/P3.3 15 P2.7/A15 31 T0/P3 P2.6/A14 T1/P3.5 P2.5/A13 ...

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... VRS51C1000 VRS51C1000 DIP-40 Pin Descriptions T 2: VRS51C1000 P D DIP40 ABLE IN ESCRIPTIONS FOR PACKAGE DIP40 Name I/O Function T2 I Timer 2 Clock Out 1 P1.0 I/O Bit 0 of Port 1 T2EX I Timer 2 Control 2 P1.1 I/O Bit 1 of Port 1 3 P1.2 I/O Bit 2 of Port 1 PWM0 ...

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... Two's complement offset byte bit Direct bit address #data 8-bit constant #data 16 16-bit constant addr 16 16-bit destination address addr 11 11-bit destination address T 4: VRS51C1000 I S ABLE NSTRUCTION ET Mnemonic Description Arithmetic instructions ADD A, Rn Add register to A ADD A, direct Add direct byte to A ...

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... VRS51C1000 Special Function Registers (SFR) Addresses 80h to FFh of the SFR address space can be accessed in direct addressing mode only. The following table lists the VRS51C1000 Special Function Registers (SFR) ABLE PECIAL UNCTION EGISTERS SFR SFR Bit 7 Register Adrs P0 80h - SP 81h - DPL 82h ...

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... In- Application Programming feature (IAP). ISP Boot Program Memory Zone The upper portion of the VRS51C1000 Flash memory can be reserved to store an ISP (In-System Programmable) boot loader program. This boot program can be used to program the Flash ...

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... See Ramtron’s website in order to download the “Versa Ware ISP” Window’s™ application which allows communication with the ISPVx firmware. The VRS51C1000 can be ordered with or without the ISPVx bootloader firmware (see Ordering information section of this Datasheet for part number information). ...

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... IAP Page Erase Function By using the IAP feature possible to perform a Page erase of the VRS51C1000 Flash memory (note that the memory area occupied by the ISP boot program cannot be page erased). Each page is 512 Bytes in size. To perform a flash page erase, the page address is ...

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... Data Memory The VRS51C1000 has total of 1KB of on-chip SRAM with a 256 byte subset of this block mapped as the internal memory structure of a standard 8052. The remaining 768 byte sub-block can be accessed using external memory addressing via the MOVX instruction. ...

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... The 768 bytes of expanded VRS51C1000 can also be accessed using the MOVX @Rn instruction (where 1). This instruction can only access data in a range of 256 bytes. The internal SRAM Control Register, RCON, allows users to select which part of the expanded SRAM will be accessed by this instruction by configuring the value of the RAMS0 and RAMS1 bits ...

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... VRS51C1000 Windowed access to all the 1KB on-chip SRAM in the range of 40h-7Fh is described in the following table. T 15: B ABLE ANK MAPPING DIRECT ADDRESSING MODE 040h~07fh BS3 BS2 BS1 BSO mapping address 000h-03Fh 040h-07Fh 080h-0BFh 0C0h-0FFh 0000h-003Fh 0040h-007Fh 0080h-00BFh 00C0h-00FFh 0100h-013Fh 0140h-017Fh 0180h-01BFh 01C0h-01FFh ...

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... Power Down mode is via a hardware Reset (note that the Watchdog Timer is stopped in Power Down). When the VRS51C1000 is in power down, its current consumption drops to about 150uA. The SMOD bit of the PCON register controls the oscillator divisor applied to the Timer 1 when used as a baud rate generator for the UART. Setting this bit to 1 doubles the UART’ ...

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... Port 2 Port P2 is similar to Port 1 and Port 3, the difference being that P2 is used to drive the A8-A15 lines of the address bus when the EA line of the VRS51C1000 is held low at reset time or when a MOVX instruction is executed. Like the P0, P1 and P3 registers, the P2 register is bit addressable ...

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... VRS51C1000 Port P0 and P2 as Address and Data Bus The output stage may receive data from two sources: The outputs of register P0 or the bus address o itself multiplexed with the data bus for P0. The outputs of the P2 register or the high byte o (A8 through A15) of the bus address for the P2 port ...

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... P4.2 1 P4.1 0 P4.0 On the VRS51C1000, the Port 4 output buffers can sink up to 20mA, which allow direct drive of LED displays. Software Port Control Some instructions allow the user to read the logic state of the output pin, while others allow the user to read the content of the associated port register. These instructions are called read-modify-write instructions ...

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... Doing so is likely to make the low-level output voltage exceed the device’s specification and it is likely to affect the device’s reliability. The VRS51C1000 I/O ports are not designed to source current. VRS51C1000 Timers The VRS51C1000 includes three 16-bit timers: Timer 0, Timer 1 and Timer 2 ...

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... VRS51C1000 Timer 0 and Timer 1 Timers 0 and 1 have four Modes of operation. These Modes allow the user to change the size of the counting register or to authorize an automatic reload when provided with a specific value. Timer 1 can also be used as a baud rate generator to generate communication frequencies for the serial interface. ...

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... VRS51C1000 T 27 (TCON) –SFR 88 ABLE IMER AND ONTROL EGISTER TF1 TR1 TF0 TR0 IE1 Bit Mnemonic Description 7 TF1 Timer 1 Overflow Flag. Set by hardware on Timer/Counter overflow. Cleared by hardware on Timer/Counter overflow. Cleared by hardware when processor vectors to interrupt routine. 6 TR1 Timer 1 Run Control Bit. Set/cleared by software to turn Timer/Counter on or off ...

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... T0PIN TR0 GATE INT0 PIN Timer 2 Timer 2 of the VRS51C1000 is a 16-bit Timer/Counter and is similar to Timers 0 and 1 in that it can operate either as an event counter timer. This is controlled by the C/T2 bit in the T2CON special function register. Timer 2 has three operating modes - Auto-Load, Capture and Baud Rate Generator ...

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... VRS51C1000 Timer 2 Capture Mode In Capture Mode, the EXEN2 bit of the T2CON register controls whether an external transition on the T2EX pin will trigger capture of the timer value. When EXEN2 = 0, Timer 2 acts as a 16-bit timer or counter, which, upon overflowing, will set the TF2 bit (Timer 2 overflow bit) ...

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... The VRS51C1000 serial port includes a double buffer for the reciever, which allows reception of a byte even if the previously received one has not been retrieved from the receive register by the processor. However, if ...

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... UART UART Operating Modes The VRS51C1000’s serial port can operate in four different Modes. In all four Modes, a transmission is initiated by an instruction that uses the SBUF register as a destination register. In Mode 0, reception is initiated by setting and REN incoming start bit initiates reception in the other modes, provided that REN is set to 1 ...

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... VRS51C1000 UART Operation in Mode 1 In Mode 1 operation, 10 bits are transmitted (through TXD) or received (through RXD). The transactions are composed of: a Start bit (Low); 8 data bits (LSB first) and one Stop bit (high). The reception is completed once the Stop bit sets the RB8 flag in the SCON register ...

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... VRS51C1000 bit register), it causes the UART’s receive controller block to perform one last shift operation: to set RI and to load SBUF and RB8. The signal to load SBUF and RB8, and to set RI, will be generated if, and only if, the following conditions are met at the time the final shift ...

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... VRS51C1000 UART Operation in Mode 3 In Mode 3, 11 bits are transmitted (through TXD) or received (through RXD). The composed of: a Start bit (Low), 8 data bits (LSB first programmable 9 data bit, and one Stop bit (High). Mode 3 is identical to Mode 2 in all respects but one: the baud rate ...

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... VRS51C1000 UART Reception in Mode 2 and Mode 3 One to zero transitions on the RXD pin initiate reception for this reason that RXD is sampled at a rate of 16 multiplied by the baud rate that has been established. When a transition is detected, the 1FFh is written into the input shift register and the divide-by-16 counter is immediately reset ...

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... VRS51C1000 The value to write into the TH1 register is defined by the following formula: SMOD TH1 = 256 - 2 x Fosc 32 x 12x (Baud Rate) Generating UART Baud Rates with Timer 2 Timer 2 is often preferred to generate the baud rate can be easily configured to operate as a 16-bit timer with auto-reload ...

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... D0h 1200bps A0h 300bps - Timer 2 Reload Value in Modes 1 & 3 for UART Baud Rate The following are examples of [RCAP2H, RCAP2L] reload values for Timer 2 when it is used as baud rate generator for the VRS51C1000 UART 22.184MHz 16.000MHz 230400bps FFFDh 115200bps FFFAh 57600bps ...

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... VRS51C1000 Interrupts The VRS51C1000 has 8 interrupt sources ( include the WDT) and 7 interrupt vectors (including reset) for handling. The interrupts are enabled via the IE register shown below –SFR A8 ABLE NTERRUPT NABLE EGISTER ET2 ES ET1 Bit Mnemonic Description 7 EA Disables All Interrupts ...

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... Interrupt Enable and Interrupt Priority When the VRS51C1000 is initialized, all interrupt sources are inhibited by the bits of the IE register being reset necessary to start by enabling the interrupt sources that the application requires. This is achieved by setting bits in the IE register, as discussed previously ...

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... VRS51C1000 Modifying the Order of Priority The VRS51C1000 allows the user to modify the natural priority of the interrupts. One may modify the order by programming the bits in the IP (Interrupt Priority) register. When any bit in this register is set gives the corresponding source a greater priority than interrupts coming from sources that don’ ...

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... WDR bit whenever an unpredicted reset has taken place. Reduced EMI Function The VRS51C1000 can also be set up for reduced EMI (electromagnetic interference) by setting bit 0 (ALEI) of the SYSCON register to 1. This function will inhibit the Fosc/6Hz clock signal output to the ALE pin. ...

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... VRS51C1000 PWM Registers - Port1 Configuration Register T 39 (PWME, $9B) ABLE ORT ONFIGURATION EGISTER 7 6 PWM4E PWM3E PWM2E 3 2 PWM0E Unused Bit Mnemonic Description 7 PWM4E When bit is set to one, the 6 PWM3E corresponding PWM pin is active as 5 PWM2E a PWM function. When the bit is 4 PWM1E ...

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... VRS51C1000 T 44: PWM (PWMD1) – SFR A7 ABLE ATA EGISTER 7 6 PWMD3.4 PWMD3.3 PWMD3 PWMD3.0 NP3.2 NP3.1 Bit Mnemonic Description 7 PWMD3.4 Contents of PWM Data Register 3 Bit 4 6 PWMD3.3 Contents of PWM Data Register 3 Bit 3 5 PWMD3.2 Contents of PWM Data Register 3 Bit 2 4 PWMD3.1 ...

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... VRS51C1000 Example of PWM Timing Diagram MOV PWMD0 #83H MOV PWME, #08H F 21: PWM T D IGURE IMING IAGRAM 1st Cycle 2nd Cycle frame frame 32T 32T 16 1T (Narrow pulse inserted by NP0[2:0]=3) PWM clock= 1/T= Fosc / 2^(PDIV+1) The SPWM output cycle frame frequency = SPWM clock/32 = [Fosc/2^(PDIV+1)]/32 If Fosc = 20MHz, PDCK[1:0] of PWMC = #03H, then PWM clock = 20MHz/2^4 = 20MHz/ ...

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... VRS51C1000 Crystal consideration The crystal connected to the VRS51C1000 oscillator input should parallel type, operating in fundamental mode. The following table provides suggested capacitor and resistor feedback values for different operating frequencies. Valid for VRS51C1000 XTAL 3MHz 6MHz open open XTAL 16MHz 25MHz ...

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... Active mode, 40MHz 15 mA Active mode 25MHz 10 mA Active mode 16MHz 10 mA Idle mode, 40MHz 7.5 mA Idle mode 25MHz 6 mA Idle mode, 16MHz 150 uA Power down mode T C ODE EST IRCUIT Vcc Vcc Icc VCC 8 PO RST EA VRS51C1000 XTAL2 (NC) XTAL1 VSS page ° C ...

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... VRS51C1000 AC Characteristics T 48 ABLE HARACTERISTICS Symbol Parameter T LHLL ALE Pulse Width T AVLL Address Valid to ALE Low T LLAX Address Hold after ALE Low T LLIV ALE Low to Valid Instruction In T LLPL ALE Low to #PSEN low T PLPH #PSEN Pulse Width T PLIV #PSEN Low to Valid Instruction In ...

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... VRS51C1000 Data Memory Read Cycle Timing The following timing diagram provides Data Memory Read Cycle timing information IGURE ATA EMORY EAD YCLE IMING T12 OSC 1 ALE #PSEN #RD PORT2 INST in Float PORT0 ______________________________________________________________________________________________ www.ramtron.com ADDRESS A15- A7-A0 Float Data in T10 T11 ...

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... VRS51C1000 Program Memory Read Cycle Timing The following timing diagram provides Program Memory Read Cycle timing information F 25 IGURE ROGRAM EMORY EAD YCLE T12 T1 OSC 1 ALE #PSEN #RD,#WR PORT2 PORT0 ______________________________________________________________________________________________ www.ramtron.com ADDRESS A15- Float A7-A0 Float INST in T9 T10 T11 ...

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... VRS51C1000 Data Memory Write Cycle Timing The following timing diagram provides Data Memory Write Cycle timing information IGURE ATA EMORY RITE YCLE IMING T12 OSC 1 ALE #PSEN #WR PORT2 INST in Float PORT0 ______________________________________________________________________________________________ www.ramtron.com ADDRESS A15- A7-A0 T10 T11 T12 T1 T2 ...

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... VRS51C1000 I/O Ports Timing The following timing diagram provides I/O Port Timing information. F 27: I IGURE ORTS IMING T7 X1 Inputs P0,P1 Inputs P2,P3 Output by Mov Current Data Px, Src RxD at Serial Port Shift Clock Mode 0 ______________________________________________________________________________________________ www.ramtron.com T8 T9 T10 T11 T12 T1 Sampled Sampled ...

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... VRS51C1000 Timing Requirement of the External Clock (VSS = 0v is assumed IGURE IMING EQUIREMENT OF XTERNAL LOCK Vdd - 0.5V 70% Vdd 20% Vdd-0.1V 0.45V External Program Memory Read Cycle The following timing diagram provides External Program Memory Read Cycle timing information IGURE XTERNAL ROGRAM ...

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... VRS51C1000 External Data Memory Read Cycle The following timing diagram provides External Data Memory Read Cycle timing information IGURE XTERNAL ATA EMORY EAD YCLE #PSEN ALE #RD TAVLL PORT 0 From Ri or DPL PORT 2 ______________________________________________________________________________________________ www.ramtron.com TLLDV TRLRH TLLYL TRLDV TLLAX TRLAZ ...

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... VRS51C1000 External Data Memory Write Cycle The following timing diagram provides External Data Memory Write Cycle timing information IGURE XTERNAL ATA EMORY RITE YCLE #PSEN ALE TLHLL #WR TAVLL A0-A7 PORT 0 From Ri or DPL PORT 2 . ______________________________________________________________________________________________ www.ramtron.com TLLYL TWLWH TQVWX TLLAX ...

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... VRS51C1000 Plastic Chip Carrier (PLCC-44) VRS51C1000 PLCC- Note: 1. Dimensions D & not include interlead Flash. 2. Dimension B1 does not include dambar protrusion/intrusion. 3. Controlling dimension: Inch 4. General appearance spec should be based on final visual inspection spec. ______________________________________________________________________________________________ www.ramtron.com 49: D PLCC- ABLE IMENSIONS OF HIP ARRIER Dimension in inch ...

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... VRS51C1000 Plastic Quad Flat Package (QFP-44) VRS51C1000 QFP- Note: 1. Dimensions D1 and E1 do not include mold protrusion. 2. Allowance protrusion is 0.25mm per side. 3. Dimensions D1 and E1 do not include mold mismatch and are determined datum plane. 4. Dimension b does not include dambar protrusion. 5. Allowance dambar protrusion shall be 0.08 mm total in excess of the b dimension at maximum material condition ...

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... VRS51C1000 Ordering Options (With ISPV2 Firmware preprogrammed) Device Number VRS51C1000-40-L-ISPV2 VRS51C1000-40-Q-ISPV2 VRS51C1000-40-P-ISPV2 VRS51C1000-40-LG-ISPV2 VRS51C1000-40-QG-ISPV2 VRS51C1000-40-PG-ISPV2 Disclaimers Right to make change - Ramtron reserves the right to make changes to its products - including circuitry, software and services - without notice at any time. Customers should obtain the most current and relevant information before placing orders. ...