Z16FMC32AG20SG Zilog, Z16FMC32AG20SG Datasheet - Page 14
Z16FMC32AG20SG
Manufacturer Part Number
Z16FMC32AG20SG
Description
Microcontrollers (MCU) 16BIT 32K FL 2K RAM 2UART 12CH 10BIT A/D
Manufacturer
Zilog
Series
Z16FMCr
Datasheet
1.Z16FMC28AG20_EG.pdf
(341 pages)
Specifications of Z16FMC32AG20SG
Processor Series
Z16FMC
Core
ZNEO
Data Bus Width
16 bit
Program Memory Type
Flash
Program Memory Size
32 KB
Data Ram Size
2 KB
Interface Type
I2C, SPI, UART
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
46
Operating Supply Voltage
2.7 V to 3.6 V
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Package / Case
LQFP-64
Development Tools By Supplier
Z16FMC28200KITG
Minimum Operating Temperature
0 C
Core Processor
ZNEO
Core Size
16-Bit
Speed
20MHz
Connectivity
I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
46
Eeprom Size
-
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
Z16FMC32AG20SG
Manufacturer:
Zilog
Quantity:
160
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List of Figures
PS028702-1210
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10. Timer Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Figure 11. PWM Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Figure 12. Edge-Aligned PWM Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Figure 13. Center-Aligned PWM Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Figure 14. LIN-UART Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Figure 15. LIN-UART Asynchronous Data Format without Parity . . . . . . . . . . . . . . 110
Figure 16. LIN-UART Asynchronous Data Format with Parity . . . . . . . . . . . . . . . . . 110
Figure 17. LIN-UART Driver Enable Signal Timing (shown with 1 Stop Bit
Figure 18. LIN-UART Asynchronous MULTIPROCESSOR Mode Data Format . . 116
Figure 19. LIN-UART Receiver Interrupt Service Routine Flow . . . . . . . . . . . . . . . 122
Figure 20. Noise Filter System Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Figure 21. Noise Filter Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Figure 22. Infrared Data Communication System Block Diagram . . . . . . . . . . . . . . 141
Figure 23. Infrared Data Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
Figure 24. Infrared Data Reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
Figure 25. ESPI Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
Figure 26. ESPI Timing When PHASE = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
Figure 27. ESPI Timing when PHASE = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
Figure 28. SPI mode (SSMD = 000) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
Figure 29. I2S mode (SSMD = 010) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
Figure 30. ESPI Configured as an SPI Master in a Single Master and Single Slave
Z16FMC Series Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Z16FMC in the 64-Pin Low-Profile Quad Flat Package (LQFP) . . . . . . . . . 7
Physical Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Endianness of Words and Quads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Alignment of Word and Quad Operations on 16-bit Memories . . . . . . . . . 16
Power-On reset Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Voltage Brownout Reset Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
GPIO Port Pin Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Interrupt Controller Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
and Parity) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
P R E L I M I N A R Y
Z16FMC Series Motor Control MCUs
Product Specification
List of Figures
xiv
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