Z16FMC32AG20EG Zilog, Z16FMC32AG20EG Datasheet - Page 196

• Manufacturer Part Number: Z16FMC32AG20EG
• Description: Microcontrollers (MCU) 16BIT 32K FL 2K RAM 2UART 12CH 10BIT A/D
• Manufacturer: Zilog
• Series: Z16FMCr

Specifications of Z16FMC32AG20EG

• Processor Series: Z16FMC
• Core: ZNEO
• Data Bus Width: 16 bit
• Program Memory Type: Flash
• Program Memory Size: 32 KB
• Data Ram Size: 2 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 46
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Package / Case: LQFP-64
• Development Tools By Supplier: Z16FMC28200KITG
• Minimum Operating Temperature: - 40 C
• Core Processor: ZNEO
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 46
• Eeprom Size: -
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Lead Free Status / Rohs Status: Details

Operation
PS028702-1210
SDA and SCL Signals
I
2
C Interrupts
The I
SLAVE mode with Master arbitration. In MASTER/SLAVE mode, it is used as the only
Master on the bus or as one of several Masters on the bus with arbitration. In a multi-Mas-
ter environment, the controller switches from MASTER to SLAVE mode on losing arbi-
tration.
Though slave operation is fully supported in MASTER/SLAVE mode, if a device is
intended to operate only as a slave, the SLAVE-ONLY mode is selected. In SLAVE-
ONLY mode, the device does not initiate a transaction even if software inadvertently sets
the START bit.
The I
significant bit first. SCL is the clock for the I
functions are selected for their respective GPIO ports, the pins are automatically config-
ured for open-drain operation.
The Master is responsible for driving the SCL clock signal. During the Low period of the
clock, a Slave holds the SCL signal Low to suspend the transaction if it is not ready to pro-
ceed. The Master releases the clock at the end of the Low period and notices that the clock
remains Low instead of returning to a High level. When the Slave releases the clock, the
I
to the amount of data transferred in one operation. When transmitting address, data or
acknowledge, the SDA signal changes in the middle of the Low period of SCL. When
receiving address, data, or acknowledge, the SDA signal is sampled in the middle of the
High period of SCL.
A low-pass digital filter is applied to the SDA and SCL receive signals by setting the filter
enable (
which is less than a system clock period in width is rejected. This filter must be enabled
when running in I
The I
request signal to the interrupt controller. If the I
interrupt is determined by bits, which are set in the I2CISTAT Register. If the I
ler is disabled, the BRG Controller is used to generate general-purpose timer interrupts.
Each interrupt source other than the baud rate generator interrupt has an associated bit in
the I2CISTAT Register, which clears automatically when software reads the register or
performs some other task such as reading or writing the data register.
2
C Master continues the transaction. All data is transferred in bytes and there is no limit
2
2
2
C Controller contains multiple interrupt sources that are combined into one interrupt
C Master/Slave Controller operates in either SLAVE-ONLY mode or MASTER/
C sends all addresses, data and acknowledge signals over the SDA line, the most-
FILTEN
) bit in the I
2
C Fast mode (400 kbps) and is also used at lower data rates.
P R E L I M I N A R Y
2
C Control Register. When the filter is enabled, any glitch,
2
C bus. When the SDA and SCL pin alternate
Z16FMC Series Motor Control MCUs
2
C Controller is enabled, the source of the
I2C Master/Slave Controller
Product Specification
2
C Control-
174