ZLF645S0P2832G Zilog, ZLF645S0P2832G Datasheet - Page 103

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ZLF645S0P2832G

Manufacturer Part Number
ZLF645S0P2832G
Description
Microcontrollers (MCU) 32K Flash 512B RAM 28 pin
Manufacturer
Zilog
Datasheet

Specifications of ZLF645S0P2832G

Data Bus Width
8 bit
Program Memory Type
Flash
Program Memory Size
32 KB
Data Ram Size
512 KB
Interface Type
ICP, UART
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
24
Number Of Timers
3
Maximum Operating Temperature
+ 70 C
Mounting Style
Through Hole
Package / Case
PDIP-28
Minimum Operating Temperature
0 C
Lead Free Status / Rohs Status
 Details
P31
PS026407-0408
P30
I
T8 TRANSMIT Mode
REF
Based on register bits CTR1[5:4], a pulse is generated at when a rising edge, falling edge,
or any edge is detected. Glitches in the input signal are filtered out if they are shorter than
the glitch filter width specified in register bits CTR1[3:2].
cuit.
The timers can be configured to operate in following modes:
Before T8 is enabled, the output of T8 depends on CTR1, bit 1. If the bit is 0, T8_OUT is
1; if it is 1, T8_OUT is 0. See
Comp.
+
+
Amp.
IR
T8 TRANSMIT Mode
T8 DEMODULATION Mode
T16 TRANSMIT Mode
T16 DEMODULATION Mode
PING-PONG Mode
P3M[1]
0
1
P20
Figure 27. Counter/Timer Input Circuit
P3M[2]
0
1
CTR1[6]
1
0
Figure
28.
Glitch Filter
Reserved
4 SCLK
8 SCLK
CTR1[3:2]
00
01
10
11
CTR1[5:4]
ZLF645 Series Flash MCUs
Figure 27
00
10
01
11
Counter/Timer Functional Blocks
Reserved
Product Specification
displays the input cir-
Edge Detection
Falling Edge
Rising Edge
CTR1[1]
CTR1[0]
95

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