ZLF645S0P2032G Zilog, ZLF645S0P2032G Datasheet
ZLF645S0P2032G
Specifications of ZLF645S0P2032G
Related parts for ZLF645S0P2032G
ZLF645S0P2032G Summary of contents
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... Crimzon Infrared Microcontrollers ZLF645 Series Flash MCUs with Learning Amplification Product Specification PS026407-0408 ® Copyright ©2008 by Zilog , Inc. All rights reserved. www.zilog.com ...
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... INFRINGEMENT RELATED IN ANY MANNER TO USE OF INFORMATION, DEVICES, OR TECHNOLOGY DESCRIBED HEREIN OR OTHERWISE. The information contained within this document has been verified according to the general principles of electrical and mechanical engineering. Z8 and Crimzon are registered trademarks of Zilog, Inc. All other product or service names are the property of their respective owners. PS026407-0408 ...
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Revision History Each instance in the revision history table reflects a change to this document from its pre- vious revision. For more details, refer to the corresponding pages or appropriate links given in the table below. Date Version Description April ...
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Table of Contents Architectural Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Register File Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Universal Asynchronous Receiver/Transmitter . . . . . . . . . . . . . . . . . . . . . . 79 Architecture . . . . . . . . . . . . . ...
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Interrupt Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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User Option Bit Shadow Register Access . . . . . . . . . . . . . . . . . . . . . . 167 User Option Byte 0 and Option Byte 0 Shadow Register Definitions ...
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... Architectural Overview Zilog’s ZLF645 Series of Flash MCU’s are members of the Crimzon microcontrollers. This series provides a directly-compatible code upgrade path to other Crimzon MCUs, offers a robust learning function, and features Flash memory and 1K general-purpose Random Access Memory (RAM). Two timers allow the generation of complex signals while performing other counting operations ...
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Interrupt Sources The ZLF645 MCU supports 23 interrupt sources with 6 interrupt vectors, as given below: • Three external interrupts. • Two from T8, T16 time-out and capture. • Three from UART Tx, UART Rx, and UART BRG. • One ...
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UART: – R and T X – 4800, 9600, 19200, and 38400 baud rates – Parity Odd/Even/None – Stop bits 1/2 • ICP (In-circuit Flash Programming) interface multiplexed with one of the GPIO’s. • Intelligent Power-On Reset (POR) ...
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Functional Block Diagram Figure 1 displays the functional blocks of the ZLF645 Flash MCU. P00 4 P01 P02 P03 Directional I/O Nibble Port 0 Programmable P04 4 P05 P06 P07 P10 P11 P12 Directional 8 P13 I/O Byte Port 1 ...
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Pin Description Figure 2 displays the pin configuration for ZLF645 MCU 20-pin QFN packages Figure 2. 20-Pin QFN Pin Configuration PS026407-0408 ZLF645 ...
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Table 3 lists the function and signal directions of each pin within the 20-pin QFN package sequentially by pin number. Table 3. 20-Pin QFN Sequential Pin Identification Pin No Symbol 1 P07 XTAL2 4 XTAL1 5 ...
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Table 4 lists the function and signal direction of each pin within the 20-pin QFN package by function. Table 4. 20-Pin QFN Functional Pin Identification Pin No Symbol 10 P00 P30 11 P01 1 P07 13 P20 14 P21 15 ...
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Figure 3 displays the pin configuration for ZLF645 MCU 20-pin PDIP, SOIC, and SSOP packages. PS026407-0408 P25 1 2 P26 P27 3 20-Pin 4 P07 PDIP SOIC XTAL2 6 SSOP 7 XTAL1 P31 8 9 P32 P33 ...
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Table 5 lists the function and signal directions of each pin within the 20-pin PDIP, SOIC, and SSOP packages sequentially by pin number. Table 5. 20-Pin PDIP/SOIC/SSOP Sequential Pin Identification Pin No Symbol 1 P25 2 P26 3 P27 4 ...
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Table 6 lists the function and signal direction of each pin within the 20-pin PDIP, SOIC, and SSOP packages by function. Table 6. 20-Pin PDIP/SOIC/SSOP Functional Pin Identification Pin No Symbol 13 P00 P30 14 P01 4 P07 16 P20 ...
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Figure 4 displays the pin configuration of the ZLF645 MCU within the 28-pin PDIP, SOIC, and SSOP packages. PS026407-0408 P25 1 2 P26 3 P27 4 P04 5 P05 6 28-Pin P06 PDIP 7 P07 SOIC SSOP ...
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Table 7 lists the function and signal directions of each pin within the 28-pin PDIP, SOIC, and SSOP packages sequentially by pin number. Table 7. 28-Pin PDIP/SOIC/SSOP Sequential Pin Identification Pin No Symbol 1 P25 2 P26 3 P27 4 ...
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Table 8 lists the functions and signal directions of each pin within the 28-pin PDIP, SOIC, and SSOP packages by function. Table 8. 28-Pin PDIP/SOIC/SSOP Functional Pin Identification Pin No Symbol 19 P00 20 P01 21 P02 23 P03 4 ...
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Figure 5 displays the pin configuration of the ZLF645 MCU within the 48-pin SSOP package. P40 P25 P26 P27 P04 P41 P05 P06 P14 P15 P07 V V P42 P16 P17 XTAL2 XTAL1 P31 P32 P33 P34 P43 V Figure ...
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Table 9. 48-Pin SSOP Sequential Pin Identification (Continued) Pin No Symbol 8 P06 9 P14 10 P15 11 P07 P42 15 P16 16 P17 17 XTAL2 18 XTAL1 19 P31 20 P32 21 ...
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Table 9. 48-Pin SSOP Sequential Pin Identification (Continued) Pin No Symbol 41 P03 42 P20 43 P21 44 P22 45 P23 46 P24 47 P46 48 P47 Table 10 lists the functions and signal directions of each pin within the ...
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Table 10. 48-Pin SSOP Functional Pin Identification (Continued) Pin No Symbol 45 P23 46 P24 2 P25 3 P26 4 P27 29 P30 19 P31 20 P32 21 P33 22 P34 26 P35 28 P36 27 P37 1 P40 6 ...
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I/O Port Pin Functions The ZLF645 MCU features up to five 8-bit ports which are described below: 1. Port 0 is nibble-programmable as either input or output. 2. Port 1 is byte-programmable as either input or output. 3. Port 2 ...
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During POR and WDT Reset, the internally generated reset drives the reset pin Low for the POR time. Any device driving the external reset line must be open-drain to avoid damage from a possible conflict during reset conditions. A pull-up ...
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Port 0 Port 8-bit bidirectional CMOS-compatible port. Its eight I/O lines are configured under software control to create a nibble I/O port. The output drivers are push/pull or open-drain, controlled by bit 2 of the If one ...
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Port 1 Port 8-bit bidirectional CMOS-compatible I/O port. It can be configured under software control as inputs or outputs. A flash programming option bit is available to connect eight pull-up transistors on this port. Bits programmed as ...
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Port 2 Port 8-bit bidirectional CMOS-compatible I/O port. Its eight I/O lines can be independently configured under software control as inputs or outputs. Port 2 is always available for I/O operation. A flash programming option bit is ...
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Port 3 Port 8-bit CMOS-compatible I/O port. Port 3 consists of four fixed inputs (P33:P30), three fixed outputs (P37:P36:P35), and one multi-functioned pin (P34) that can function as an output only bidirectional open-drain I/O ...
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Figure 9 displays the Port 3 configuration. ZLF645 FLASH MCU P31 can be used as an interrupt, analog comparator input, infrared learning amplifier input, normal digital input pin, and as a Stop Mode Recovery source. When bit 2 of the ...
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COMP1 is used. The reference voltage for COMP1 is P30 (P mode, P30 cannot be read as a digital input when the CPU reads bit 0 of the Port 3 register; such reads always return a value of 1. Also, ...
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Table 12. Summary of Port 3 Pin Functions In-Circuit Pin I/O Programmer Counter/Timers P30 IN P31 IN P32 IN P33 IN P34 IN/OUT ICP P35 OUT P36 OUT P37 OUT Port 3 also provides output for each of the ...
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P34 Data T8_Out P3M D2 P31 + – IR1 I REF P3M D1 + – P30 Comp1 P32 P33 Figure 10. Port 3 Counter/Timer Output Configuration PS026407-0408 CTR0, bit 0 PCON, bit 0 MUX MUX CTR2, bit ...
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Comparator Inputs In ANALOG mode, P31 and P32 have a comparator front end. The comparator reference is supplied by P33 and P corresponding IRQ1 are diverted to the Stop Mode Recovery sources (excluding P31, P32, and P33) as displayed in ...
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ZLF645 FLASH MCU Open-Drain I/O Out In PS026407-0408 Port 4 (I/O) Figure 11. Port 4 Configuration ZLF645 Series Flash MCUs Product Specification V DD Resistive pull-up transistor Flash Programming Option Pad Port 4 29 ...
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Port Configuration Register The Port Configuration register (see comparator output on Port 3. The PCON register is located in expanded register Bank F, address 00h. Table 13. Port Configuration Register (PCON) Bit Reserved Field ...
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Port 0/1 Mode Register The Port 0/1 Mode register (see Port 1. The Port 0 direction is nibble-programmable. Bit 6 controls the upper nibble of Port 0, bits [7:4]. Bit 0 controls the lower nibble of Port 0, bits [3:0]. ...
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Port 0 Register The Port 0 register (see Table 15. Port 0 Register (P0) Bit 7 6 P07 P06 Field X X Reset R/W R/W R/W Address Bit Position R/W Description [7] Port 0 Pin 7—Available for I/O if UART ...
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Port 1 Register The Port 1 register (see Table 16. Port 1 Register (P1) Bit 7 6 P17 P16 Field X X Reset R/W R/W R/W Address Note: For package types other than the 48-pin package, this register is available ...
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Port 2 Mode Register The Port 2 Mode register (see Bit 0 of the Port 3 Mode register determines whether the output drive is push/pull or open-drain. Table 17. Port 2 Mode Register (P2M) Bit 7 6 P27 I/O P26 ...
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Port 2 Register The Port 2 register (see Table 18. Port 2 Register (P2) Bit 7 6 P27 P26 Field X X Reset R/W R/W R/W Address Bit Position Value Description [7:0] Port 2 Pins 7–0—Each bit provides access to ...
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Port 3 Mode Register The Port 3 Mode register (see inputs and the output mode of Port 2. When bit 2 is set, the IR Learning Amplifier is used instead of the COMP1 comparator, regardless of the value of bit ...
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Port 3 Register The Port 3 register (see write access to the port pins P37 through P34. Table 21. Port 3 Register (P3) Bit 7 6 P37 P36 Field 0 0 Reset R/W R/W R/W Address Bit Position Value Description ...
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Bit Position Value Description [3] Read Port 3, Pin 3 Input—Writing this bit has no effect. If P3M[1]=0: 0 P33 is Low. 1 P33 is High. If P3M[1]=1 or SMR4[4]=1: 0 SMR condition exists. 1 SMR condition does not exist. ...
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Port 4 Mode Register The Port 4 Mode register (see Bit 3 of the Port Configuration register (PCON) determines whether the output drive is push/pull or open-drain. Table 22. Port 4 Mode Register (P4M) Bit 7 6 P47 I/O P46 ...
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Port 4 Register The Port 4 register (see Table 23. Port 4 Register (P4) Bit 7 6 P47 P46 Field X X Reset R/W R/W R/W Address Bit Position Value Description [7:0] Port 4 Pins 7–0—Each bit provides access to ...
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Memory and Registers ® The Z8 LXMC CPU used in the ZLF645 Series of Flash MCUs incorporates special features to extend the available memory space while maintaining the benefits CPU core in battery-operated applications. Flash Program/Constant Memory ...
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Register File The ZLF645 Series of Flash MCUs features up to 1024 bytes of register file space, organized in 256-byte banks. Bank 0 contains 235 or 237 bytes of RAM addressed as general purpose registers port addresses, ...
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RAM memory. This enables the entire 1K or 512 B, depending on the product, of the RAM memory to be used for the stack. 8-bit Stack Addressability For 8-bit stack addressability, only the SPL register ...
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RP=00: selects Register Bank 0, Working Register Group 0 PS026407-0408 Active Group Active Bank The ...
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Register Pointer Example R253 RP = 00h R0 = Port Port Port Port Port 4 But if: R253 RP = 0Dh R0 = CTR0 R1 = CTR1 R2 ...
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Example For example, the following code uses linear addressing for the source of a register transfer operation and uses a working register address for the target: SRP #%23 LD R0, #%55 SRP #%12 LD R6, #%03 LD R7, #%20 LD ...
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Banks 1-3 Bank 0 CPU Control F0h-FFh General Purpose Registers 05h-EFh Ports 00h-04h ** ** For 20 and 28 pin parts, the Port01 and Port04 locations become available for use as general purpose registers Figure 15. Register File LDX, LDXI ...
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Register Pointer Register The upper nibble of the Register Pointer register (see register group is accessed. A working register group consists of 16 bytes. The lower nibble selects the expanded register file bank; for ZLF645 MCU, Banks ...
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... When ZLF645 MCU is not in 16-bit stack pointer mode, this register is available to store use user data and its functionality is identical to other Zilog products such as the ZLP12840 and ZLR64400 MCUs. When available for user data, this register must not be used as a counter for the DJNZ instruction. ...
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Register File Summary Table 27 lists each linear (12-bit) register file address to the associated register, mnemonic, and reset value. The table also lists the register bank (or banks) and corresponding 8-bit address (if any) for each register and a ...
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Table 27. Register File Address Summary (Continued) Address (Hex) 12-Bit Bank 8-Bit Register Description 0F9 All F9 Interrupt Priority Register 0FA All FA Interrupt Request Register 0FB All FB Interrupt Mask Register 0FC All FC Flags Register 0FD All FD ...
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Table 27. Register File Address Summary (Continued) Address (Hex) 12-Bit Bank 8-Bit Register Description D09 D 09 Timer 16 Capture High Register D0A D 0A Timer 8 Capture Low Register D0B D 0B Timer 8 Capture High Register D0C D ...
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ICP Interface The ICP interface of the ZLF645 is a single pin RS-232 like interface for performing programming, reads, and memory erasures to the ZLF645’s Flash memory. For enabling the ZLF645 into ICP mode and for performing ICP operations, the ...
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Enabling Flash Accesses Through the ICP After the ZLF645 is in ICP mode, the programmed to 1 before Flash accesses are enabled through the ICP interface. ICP Interface Logic Architecture The ICP logic within the ZLF645 MCU consists of four ...
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Caution: For operation of the ICP, all power pins (V and all ground pins (V RS-232 TX RS-232 RX Figure 17. Interfacing the In-Circuit Programming Pin P34 with an RS-232 Interface (2) ICP Data Format The ICP interface uses the ...
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For optimal operation with asynchronous datastreams, the maximum recommended baud rate is the system clock frequency divided by 8. The maximum possible baud rate for asynchronous datastreams is the system clock frequency divided by 4, but this theoretical maximum is ...
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As the ICP interface uses a single pin for both receive and transmit, it can only receive or transmit at a given time. For the most part, this is not a problem, as the ICP uses a host driven protocol ...
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Table 29. In-Circuit Programmer Commands (Continued) Command ICP Command Byte Read Flash Controller 09H Registers Write Flash Memory 0AH Read Flash Memory 0BH Reserved 0CH – 0DH Read Program Memory CRC 0EH Reserved 0FH –1AH Read ICP Autobaud Register 1BH ...
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This command when executed returns a value of assigned for the ZLF645 MCU. • Read ICP Status Register (02H) ICPSTAT register. ← ICP 02H → ICP ICPSTAT[7:0] • Write ICP Control Register (04H) the data that follows the command to ...
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The on-chip Flash Controller must be written to and unlocked for the programming operation to occur. If the Flash Controller is not unlocked, the data is discarded. Also, data is ...
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ICP Autobaud[7:0] • Write Test Mode Register (F0H)— The Write Test Mode Register command writes the data that follows the command to the ← ICP F0H ← ICP TESTMODE[7:0] • Read Test Mode Register (F1H)— The Read Test Mode ...
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ICP Status Register The ICP Status register (see the ICP and the device. Table 31. ICP Status Register (ICPSTAT) Bits 7 6 FLASHCTL FLPROT1 Field 0 0 Reset R R R/W Bit Position Value Description [7] FLASHCTL —When read, this ...
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TEST Mode Register The TEST Mode register is used to enable various device test or Flash memory access modes. At present this register only provides configuration for a single mode where, once programmed, Flash memory accesses bypass the devices Flash ...
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... In addition to the Flash main memory, there is a 256-byte Information block, arranged as 4 rows of 64 bytes. Each row is defined as a page. User access is only allowed to Page 3, where user definable Option bits reside. Pages 2-0 are for Zilog Note: Information block does not have a Flash contents sector protection mechanism. ...
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... Address locations code of . This pass code is programmed by Zilog 5Ah is an indication that the Flash memory passed Flash testing. The Flash read/write protect bits in Byte 1 control the level of Page 3 access allowed to the User along with the User’s level of access to the Flash’s main memory. Bytes ...
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... Pages 0 through 2 (addresses ® for Zilog internal use and are inaccessible by user or programmer vendor, either through the ICP interface or by using the Flash Byte Programming interface. Flash Controller Operation The Flash Controller provides the appropriate Flash controls and timing for byte/word programming, Page Erase, Mass Erase, and reading of the Flash memory for Flash accesses made by either the CPU or through the ICP interface ...
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Reset Lock State 0 Write Page Select Register Write FCTL No 73H Yes Lock State 1 Write FCTL No 8CH Yes Write Page Select Register No Page Select values match? Yes Yes Page in Protected Sector? No Page Unlocked Program/Erase ...
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Flash Operation Timing Using Flash Frequency Registers Before a program or erase operation on Flash memory, you must first configure the Flash frequency High and Low Byte registers. The Flash frequency registers allow programming and erasing of the Flash with ...
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If the two writes match, the selected page becomes active. See After unlocking a specific page, you can enable either Page Program or Page Erase. For Flash main memory, writing ...
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The programming operation can only be used to change bits from change a Flash bit (or multiple bits) from requires execution of either the Page Erase or Mass Erase commands. Byte Programming can ...
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Flash Control Register Definitions Flash Control Register The Flash Controller must be unlocked using the Flash Control register (see before programming or erasing the Flash memory. Writing Flash Control register unlocks the Flash Controller. When the Flash Controller is unlocked, ...
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Flash Status Register The Flash Status register (see This register can be read any time. The read-only Flash Status register shares its Register File address with the Write-only Flash Control register. Table 35. Flash Status Register (FSTAT) Bits 7 6 ...
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Table 36. Flash Page Select Register (FPS) Bits 7 6 IFEN Field 0 0 Reset R/W R/W R/W Address Bit Position Value Description [7] IFEN —Information Area Enable 0 Operation to be performed on Flash main memory. 1 Operation to ...
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Bit Position Value Description [7:0] SPROT7-SPROT0 —Sector Protection Each bit corresponds to an 16-page Flash sector. For the ZLF645xxxxx64, all bits are used. Only bits 3-0 are used in the ZLF645xxxxx32. Flash Frequency High and Low Byte Registers The Flash ...
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Table 39. Flash Frequency Low Byte Register (FFREQL) Bits 7 6 Field Reset R/W Address Bit Position Value Description [7:0] FFREQL —Flash Frequency Low Byte Low byte of the 16-bit Flash Frequency value. Flash Controller Functions Summary The Flash Controller ...
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... Flash programming by third party vendors who manufacture gang programmers. For more information on how to use this interface, refer to Third-Party Flash Programming Support for Z8 Crimzon Flash Parts, available for download at www.zilog.com. Enabling The Flash Byte Programming Interface The Flash Byte Programming Interface is enabled by writing three bytes to the ICP interface: 1. 80H — ...
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Table 41.Flash Byte Programming Functions Summary Flash Memory Program Block Main Yes Memory Main No Memory Main 1 Yes Memory Information 2 Yes Area Information No Area Information No Area Notes 1. Program, Read, and Page Erase access is limited ...
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Infrared Learning Amplifier The ZLF645 MCU’s infrared learning amplifier allows you to detect and decode infrared transmissions directly from the output of the receiving diode without the need for external circuitry (see Port diode can be connected ...
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Universal Asynchronous Receiver/ Transmitter The Universal Asynchronous Receiver/Transmitter (UART full-duplex communication channel capable of handling asynchronous data transfers. The two UARTs use a single 8-bit data mode with selectable parity. The UART interface when enabled uses the GPIO ...
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Architecture The UARTs consist of three primary functional blocks: transmitter, receiver, and Baud Rate Generator. The UART transmitter and receiver function independently, but employ the same baud rate and data format. RxD Receive Shifter Receive Data Register System Bus Transmit ...
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Data Format The UART transmits and receives data in an 8-bit data format, with the least significant bit (lsb) occurring first. An even- or odd-parity bit can be optionally added to the data stream. Each character begins with an active ...
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Check the Transmit Status register bit, UST[2], to determine if the Transmit Data register is empty (indicated by 1). If empty, continue to register is full (indicated by 0), continue to monitor the UST[2] bit until the Transmit Data ...
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Before disabling the transmitter, read the transmit completion status bit, UST[1]. If UST[1]=0, continue to monitor the bit until it changes to 1, which indicates that all data in the Transmit Data and Internal Shift registers has been transmitted. ...
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The UART is now configured for interrupt-driven data reception. When the UART Receiver interrupt is detected, the associated ISR performs the following: 1. Checks the UART Status register to determine the source of the interrupt, whether error, ...
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Receive Data register. If data is present in the Receive Data register, an interrupt will occur after the UART Receive Data register is read. • An overrun is detected—An overrun occurs ...
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Read Data Figure 25. UART Receiver Interrupt Service Routine Flow PS026407-0408 ZLF645 Series Flash MCUs Receiver Ready Receiver Interrupt Read Status No Errors? Yes Read Data that clears the RDA bit and resets the error bits Discard Data Product Specification ...
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Baud Rate Generator Interrupts If the BRG interrupt enable is set, the UART Receiver interrupt asserts when the UART Baud Rate Generator reloads. This action allows the BRG to function as an additional counter if the UART functionality is not ...
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Follow the steps below to configure the BRG as a timer with interrupt on time-out: 1. Disable the UART by clearing the receive and transmit enable bits, UCTL[7: Load the appropriate 8-bit count value into the UART ...
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UART Receive Data Register/UART Transmit Data Register The UART Receive/Transmit Data register (see from the UART channel. When the UART receives a data byte, it can be read from this register. The UART receive interrupt is cleared when this register ...
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Bit Position Value Description [6] Parity Error —Set when a parity error occurs; cleared when URDATA is read parity error occurs. 1 Parity error occurs. [5] Overrun Error—Set when an overrun error occurs; cleared when URDATA is read. ...
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Table 46. UART Control Register (UCTL) Bit 7 6 Transmitter Receiver Enable Enable Field 0 0 Reset R/W R/W R/W Address Bit Position Value Description [7] 0 Transmitter disabled. 1 Transmitter enabled. [6] 0 Receiver disabled. 1 Receiver enabled. [5] ...
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The system clock is usually the crystal clock divided by 2. When the UART baud rate gen- erator is used as an additional timer, a Read from this register returns the actual value of the count of the BRG in ...
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Timers The ZLF645 MCU infrared timer features a 16-bit and an 8-bit counter/timer, each of which can be used simultaneously for transmitting. Both timers can be used for demodu- lating an input carrier wave and share a single input pin. ...
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Table 48 summarizes the timer control registers. Some timer functions can also be affected by control registers for other peripheral functions. Table 48. Timer Control Registers Address (Hex) 12-Bit Bank 8-Bit Register Description D00 D 00 Counter/Timer 8 Control Register ...
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Based on register bits CTR1[5:4], a pulse is generated at when a rising edge, falling edge, or any edge is detected. Glitches in the input signal are filtered out if they are shorter than the glitch filter width specified in ...
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Reset T8_ENABLE Bit Load TC8L Reset T8_OUT Set Time-Out Status Bit (CTR0 bit 5) and generate TIMEOUT_INT if enabled Single Pass Load TC8L Reset T8_OUT Figure 28. TRANSMIT Mode Flowchart PS026407-0408 T8 (8-Bit) TRANSMIT Mode No T8_Enable Bit Set CTR0, ...
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When T8 is enabled, the output T8_OUT switches to the initial value (CTR1, bit 1). If the initial value (CTR1, bit TC8L is loaded; otherwise, TC8H is loaded into the counter. In SINGLE-PASS mode (CTR0, bit 6), ...
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Notes: 1. The “h” suffix denotes hexadecimal values. 2. Transition from 0 to Caution: Using the same instructions for stopping the counter/timers and setting the status bits is not recommended. Two successive commands are necessary. First, the counter/timers must be ...
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T8 DEMODULATION Mode You must program TC8L and TC8H to ing, falling, or both depending on CTR1 bits [5:4]) is detected, it starts to count down. When a subsequent edge (rising, falling, or both depending on CTR1 bits [5:4]) is ...
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Figure 32. DEMODULATION Mode Count Capture Flowchart When bit 4 of CTR3 is enabled, the flow of the demodulation sequence is altered. The third edge makes T8 active, and the fourth and fifth edges are captured. The capture interrupt is ...
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Disable T8 PS026407-0408 T8 (8-Bit) DEMODULATION Mode T8_Enable CTR0, D7? No Yes %FF TC8 First Edge Present? No Yes Enable TC8 T8_Enable Bit Set? No Yes No Edge Present? Yes Set Edge Present Status Bit and Trigger Data Capture Int. ...
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Disable T8 Figure 34. DEMODULATION Mode Flowchart with Bit 4 of CTR3 Set PS026407-0408 ZLF645 Series Flash MCUs T8 (8-Bit) DEMODULATION Mode T8_Enable CTR0 bit 7 No Yes FFh TC8 Third Edge Present No Yes Enable TC8 T8_Enable Bit Set ...
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T16 TRANSMIT Mode In NORMAL or PING-PONG mode, the output of T16 when not enabled depends on CTR1, bit 0. If this bit is set to 0, T16_OUT set to 1, T16_OUT is 0. You can ...
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Caution: Do not load these registers at the time the values are to be loaded into the counter/timer to ensure known operation. An initial count not allowed. An initial count of 0 causes T16 to count from ...
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If Bit 6 of CTR2 Is 0— CTR1 bits [5:4]) is detected during counting, the current count in T16 is complemented and loaded into HI16 and LO16. When data is captured, one of the edge detect status bits (CTR1, bit ...
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Enable TC8 Enable Initiating PING-PONG Mode First, ensure that both counter/timers are not running. Follow the steps below to initiate the PING-PONG mode: 1. Set T8 into SINGLE-PASS mode (CTR0, bit 6) 2. Set T16 into SINGLE-PASS mode (CTR2, bit ...
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CTR2 is set. When bit 6 of CTR1 is set, P36 outputs the logic combination of T8_OUT and T16_OUT via bits [4:5] of CTR1. T8_OUT T16_OUT MUX CTR1 data bit 2 CTR1 data bit 3 PS026407-0408 P34_INTERNAL P36_INTERNAL ...
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Counter/Timer Registers The following sections describe each of the Timer/Counter registers in detail. Timer 8 Capture High Register The Timer 8 Capture High register (see of the 8-bit Counter/Timer 0. This register contains the number of counts when the input ...
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Table 50. Timer 8 Capture Low Register (LO8) Bit 7 6 Field 0 0 Reset R R R/W Address Bit Position Value Description [7:0] 0hh–FFh T8_Capture_LO —Read returns captured data. Writes have no effect. Timer 16 Capture High Register The ...
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Timer 16 Capture Low Register The Timer 16 Capture Low register (see output of the 16-bit Counter/Timer 16. This register contains the least significant byte (LSB) of the data. Note: This register is not reset after a Stop Mode Recovery. ...
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Counter/Timer 16 Low Hold Register The Counter/Timer 16 Low Hold register (see loaded into the T16 timer. This register is not reset after a Stop Mode Recovery. Note: Table 54. Counter/Timer 16 Low Hold Register (TC16L) Bit 7 6 Field ...
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Counter/Timer 8 Low Hold Register The Counter/Timer 8 Low Hold register (see while the T8 output is 0. This register is not reset after a Stop Mode Recovery. Note: Table 56. Counter/Timer 8 Low Hold Register (TC8L) Bit 7 6 ...
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Counter/Timer 8 Control Register The Counter/Timer 8 Control register (see T8 timer. Writing 1 to CTR0[5] is the only way to reset the Terminal Count status condition. Reset Caution: this bit before using/enabling the counter/timers. Note: You must be careful ...
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Bit Position Value Description [4:3] T8 _Clock —Select the T8 input clock frequency. These bits are not reset upon Stop Mode Recovery. 00 SCLK 01 SCLK ÷ SCLK ÷ SCLK ÷ 8 [2] Capture_INT_Mask —Disable/enable interrupt ...
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T8 and T16 Common Functions Register The T8 and T16 Common Functions register (CTR1) controls the functions in common with Timer 8 and Timer 16. Be careful to differentiate TRANSMIT mode from DEMODULATION mode, as set by Note: CTR1[7]. The ...
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Bit Position Value Description [5:4] TRANSMIT Mode T8/T16 Logic—Defines how the Timer 8/Timer 16 outputs are combined logically. These bits are not reset upon Stop Mode Recovery. 00 Output is T8 AND T16. 01 Output T16. 10 ...
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Bit Position Value Description [1] TRANSMIT Mode Initial Timer 8 Out—Select the initial T8_OUT state when Timer 8 is enabled. While the timer is disabled, the opposite state is asserted on the pin to ensure that a transition occurs when ...
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Counter/Timer 16 Control Register Table 59 describes the bits for the Counter/Timer 16 Control register (CTR2). Table 59. Counter/Timer 16 Control Register (CTR2) Bit 7 6 Single/ T16_Enable Field Modulo Reset R/W R/W R/W Address Bit Position Value ...
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Bit Position Value Description [2] Capture_INT_Mask —Disable/enable interrupt when data is captured into either LO16 or HI16 upon a positive or negative edge detection in DEMODULATION mode. This bit is not reset upon Stop Mode Recovery. 0 Disable data capture ...
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Bit Position Value Description [4] T16_Out Disable —Set this bit to disable toggling of the Timer 16 output. Time- out interrupts are still generated. This bit is not reset upon Stop Mode Recovery. 0 T16 toggles normally. 1 T16 toggle ...
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Interrupts The ZLF645 MCU features six interrupts (see maskable and prioritized (see The six interrupt sources are divided as follows: • Three sources are claimed by Port 3 lines P33:P31 • Two by the counter/timers (see • One for low-voltage ...
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P32 UCTL bits 5 & P31 Interrupt Edge IRQ Register (bits 6 & 7) IRQ2 Interrupt Request PS026407-0408 UART R P33 Stop Mode Recovery Source X P3M[1] OR SMR4[ Timer 16 Select IRQ0 ...
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Table 62. Interrupt Types, Sources, and Vectors Name Source IRQ0 P32, UART Rx IRQ1 P33, UART Tx, BRG, SMR Event IRQ2 P31 IRQ3 Timer 16 IRQ4 Timer 8 IRQ5 Low-Voltage Detection When more than one interrupt is pending, priorities are ...
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Programming bits for the Interrupt Edge Select are located in the IRQ register (R250), bit 6 and bit 7. Table 63 Table 63. Interrupt Request Register IRQ Bit Note: F ...
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Bit Position Value Description {[4:3], [0]} Group Priority 000 Reserved 001 C > A > B 010 A > B > C 011 A > C > B 100 B > C > A 101 C > B > A ...
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Bit Position Value Description [5] Read IRQ5 (Low-Voltage Detection) 0 Interrupt did not occur. 1 Interrupt occurred. Write 0 Clear interrupt. 1 Set interrupt. [4] Read IRQ4 (T8 Counter) 0 Interrupt did not occur. 1 Interrupt occurred. Write 0 Clear ...
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Interrupt Mask Register Bits [5:0] are used to enable the interrupt. Bit 7 is the status of the master interrupt. When reset, all interrupts are disabled. When writing 1 to bit 7, you must also execute the EI instruction to ...
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PS026407-0408 ZLF645 Series Flash MCUs Product Specification 128 ...
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... MHz *Note: preliminary value, including pin parasitics. Zilog’s IR MCU supports crystal, resonator, and oscillator. Most resonators have a frequency tolerance of less than ±0.5%, which is enough for a remote control application. Resonator has a very fast startup time, which is around few hundred microseconds. Most crystals have a frequency tolerance of less than 50 ppm (± ...
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... Zilog recommends not to use more than 10 pF loading capacitor for the crystal. If the stray capacitance of the PCB or the crystal is high, the loading capacitance C1 and C2 must be reduced further to ensure stable oscillation before the T 5-6 ms. For more details, see For Stop Mode Recovery operation, bit 5 of SMR register allows you to select the Stop Mode Recovery delay, which is the T MCU executes instruction immediately after it wakes up from the STOP mode ...
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OSC PS026407-0408 ZLF645 Series Flash MCUs User Option Byte 1, Bit # Figure 42. SCLK/TCLK Circuit Internal Clock Signals (SCLK and TCLK) Product Specification 131 SMR[0] 0 SCLK TCLK 1 ...
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Reset and Power Management The ZLF645 MCU provides the following reduced-power modes, power monitoring, and reset features: • Voltage Brownout Standby—Stops the oscillator and internal clock when the power level drops below the VBO low voltage detect point. Initiates a ...
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Table 67. Reset and Power Management Registers (Continued) Address (Hex) 12-Bit Bank 8-Bit Register Description F0E F 0E Stop Mode Recovery Register 3 F0F F 0F Watchdog Timer Mode Register 5-Clock Filter XTAL Internal CLK RC Oscillator Low Operating V ...
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Voltage Brownout Standby An on-chip voltage comparator circuit (VBO) checks that the V for correct operation of the device in terms of Flash memory reads. A second on-chip comparator circuit (subVBO) checks that the V tion of the VBO circuit. ...
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To enter HALT mode, first flush the instruction pipeline to avoid suspending execution in mid-instruction. Execute a NOP instruction (OpCode = appropriate sleep instruction, as given below Power consumption during HALT mode can be reduced by first setting ...
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Bit Position Value Description [1] 0 LVD clear. 1 Low-voltage detected (V [0] 0 Voltage detection disabled. 1 Voltage detection enabled. Power-On Reset Timer When power is initially applied to the device, a timer circuit clocked by a dedicated on-board ...
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WDTMR register cannot be read. The register is located in Bank F of the Expanded Reg- ister Group at address location Note: This register is not reset after a Stop Mode Recovery. Table 69. Watchdog Timer Mode Register (WDTMR) Bit ...
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Power-On Reset defaults. A Stop Mode Recovery restores most registers to their Power-On Reset defaults. Register bits not reset by a Stop Mode Recovery are highlighted in grey in the register tables. Register bit SMR[7] is set to ...
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SMR Register Events The SMR register function is similar to the standard Stop Mode Recovery feature used in ® previous Z8 CPU-compatible parts. Register bits SMR[4:2] are set to select one of six event modes, as displayed in is compared ...
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SMR[4:2] = 000 V CC SMR[4:2] = 010 P31 SMR[4:2] = 011 P32 SMR[4:2] = 100 P33 SMR[4:2] = 101 P27 SMR[4:2] = 110 P20 P23 SMR[4:2] = 111 P20 P27 SMR[6] Figure 44. SMR Register-Controlled Event Sources PS026407-0408 ZLF645 ...
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Table 70. Stop Mode Recovery Register (SMR) Bit 7 6 Stop Stop Mode Field Flag Recovery Level 0 0 Reset R W R/W Address Bit Position Value Description [7] Stop Flag —Indicates whether last startup was power-on reset or ...
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Bit Position Value Description [1] SMR Short Reset Time —Controls whether the devices SMR reset period is equivalent to the RC oscillator based POR reset period or whether it depends on the detection of XTAL1 clock oscillation. 0 Unless SMR[5]=1, ...
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After the following example code is executed P20 will wake the part from STOP mode: LD P2M, #%FF SRP #%0F LD SMR1, #%01 SRP #%00 LD P2, #%00 NOP STOP After the following example code is executed ...
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Individual Port 2 Pin SMR Logic Bit P2M [n] Bit SMR1 [n] Port 2, Pin n D Bit P2[n] Port 2 Read/Write P20 Logic P21 Logic P22 Logic P23 Logic P24 Logic SMR1 P25 Logic ...
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Table 71. Stop Mode Recovery Register 1 (SMR1) Bit 7 6 P27 Stop P26 Stop Field Select Select 0 0 Reset W W R/W Address Bit Position Value Description [7] 0 P27 not selected. 1 P27 selected as an SMR ...
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The logic configured by the SMR2 register ignores any port pins that are configured as an output, or that are selected as source pins in registers SMR1 or SMR3. The SMR2 register is summarized in SMR2[4:2] = 000 V CC ...
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Table 72. Stop Mode Recovery Register 2 (SMR2) Bit 7 Reserved Stop Mode Recovery Field X Reset — R/W Address Bit Position Value Description [7] — Reserved —Read is undefined; write must be 0. [6] Stop Mode Recovery Level 2 ...
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To configure a Port 3 input pin as an SMR3 event source set the corresponding SMR3 register bit. By default, a Stop Mode Recovery event occurs when the pin’s state is zero. After a Port 3 pin is configured as ...
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Individual Port 3 Pin SMR Logic Bit SMR3 [n] Port 3, Pin n D Bit P3[n] Port 3 Read/Write P30 Logic P31 Logic P32 Logic P33 Logic SMR3 Figure 47. SMR3 Register-Controlled Event Sources PS026407-0408 ...
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Table 73. Stop Mode Recovery Register 3 (SMR3) Bit 7 6 — Field X X Reset — — — R/W Address Bit Position Value Description [7:4] — Reserved —Reads undefined; Must be written to 1. [3] 0 P33 not selected. ...
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Stop Mode Recovery Register 4 The Stop Mode Recovery register 4 (see indicates the reference value status for registers SMR1 and SMR3. Table 74. Stop Mode Recovery Register 4 (SMR4) Bit 7 6 Reserved Field X X Reset — — ...
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Z8 LXMC CPU Programming Summary The following sections provide a summary of information useful for programming the Z8 LXMC CPU included in this device. For more details on the Z8 LXMC CPU and its instruction set, refer to Z8 Addressing ...
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Table 75. Symbolic Notation for Operands (Continued) Assembly Symbol Operand Description RR1 % aa Register Pair (8-bit Address) RR2 RR1 or RR2 represents the 8-bit address of a register pair. For addresses 00h–DFh or F0h–FFh , the equivalent 12-bit address ...
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Table 75. Symbolic Notation for Operands (Continued) Assembly Symbol Operand Description DA Direct Address (JP, CALL) LABEL CALL operand 16-bit Program Memory address in the range of 0000H to FFFFH . DA replaces ...
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Table 76. Additional Symbols (Continued) Symbol ↔ ~ Flags Register The Flags register (see bits of status information. Table 77. Flags Register (FLAGS) Bit Field X X Reset R/W R/W R/W Address Bit Position Value Description ...
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Bit Position Value Description [3] Decimal Adjust Flag (D) Used for binary-coded decimal (BCD) arithmetic. 0 Flag Clear 1 Flag Set [2] Half Carry Flag (H) Set when a carry out of or borrow into bit arithmetic ...
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Table 78. Condition Codes (Continued) Assembly Binary Hex Mnemonic 0111 7 C 0111 7 ULT 1000 8 T (or blank) 1001 9 GE 1010 A GT 1011 B UGT 1100 C NOV 1101 D PL 1110 E NZ 1110 E ...
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Electrical Characteristics Absolute Maximum Ratings A stress greater than listed in Functional operation of the device at any condition outside those indicated in the operational sections of these specifications is not implied. Exposure to absolute maximum rating conditions for extended ...
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Standard Test Conditions The characteristics listed in this product specification apply for standard test conditions. All voltages are referenced to Ground. Positive current flows into the referenced pin (see Figure 48). Capacitance Table 80 lists the capacitance. Table 80. Capacitance ...
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DC Characteristics Table 81 describes the direct current (DC) characteristics of the ZLF645 Flash MCU. Table 81. DC Characteristics Symbol Parameter 1 V Supply Voltage CC V Clock Input High CH Voltage V Clock Input Low CL Voltage V Input ...
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Table 81. DC Characteristics (Continued) Symbol Parameter Standby Current CC1 (HALT mode Standby Current CC2 (STOP mode Standby Current LV (Low Voltage Low Voltage BO cc Protection V V Low Voltage ...
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... DETHI guaranteed to be detected (see Note 6) Notes ® 1. Zilog recommends adding a filter capacitor (minimum 0.1 voltage fluctuations are anticipated, such as those resulting from driving an infrared LED. 2. All outputs unloaded, inputs at rail. 3. CL1 = CL2 = 100 pF. 4. Oscillator stopped. 5. Oscillator stops when V falls below For reference, under typical process, 25 ° ...
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AC Characteristics Figure 49 and Table 82 MCU. Clock IRQ N 8 Clock Setup Stop-Mode Recovery Source PS026407-0408 lists the alternating current (AC) characteristics of ZLF645 Flash ...
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Table 82. Clock, Reset, Timers, and SMR Timing No Symbol Parameter Input Clock Period Clock Input Rise and Fall Times Input Clock Width W 4 ...
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Table 82. Clock, Reset, Timers, and SMR Timing (Continued) No Symbol Parameter 13 T Power-on reset POR 14 f Frequency of input iramp signal for IR amplifier Notes 1. Timing Reference uses 0 Interrupt request through Port ...
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Flash Option Bits Programmable Flash Option Bits allow user configuration of certain aspects of ZLF645 MCU functionality. This configuration data is stored in the Flash memory Information Block and then read into option byte shadow registers during the last portion ...
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The Option Bit Shadow registers are part of the ZLF645’s Register File and are accessible for read/write access. User Option Bit Locations in Flash Memory The user option bits are located in the upper two bytes of the Information block, ...
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P2PU = 1: Port 2 Pull-ups disabled. P2PU = 0: Port 2 Pull-ups enabled. P1HPU = 1: Port 1 high nibble Pull-ups disabled P1HPU = 0: Port 1 high nibble Pull-ups enabled. P1LPU = 1: Port 1 low nibble Pull-ups ...
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Table 86. User Option Byte 1 (OPT1) Bit 7 Field 1 Erased State Flash Address Bit Position Value Description [7:4] — Reserved [3] 16BITSTK —16 bit Stack Pointer Addressiblity Enable 1 The ZLF645 is enabled for 8-bits of stack pointer ...
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FLRWP —Flash Main Memory Protect 1 Flash Main Memory and Information Area Page 3 can be read, programmed, and erased by both the Flash Byte Programming interface or through the ICP interface. Reads and writes to the Flash main ...
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Packaging Figure 50 displays the 20-pin quad flat no-lead (QFN) package for the ZLF645 Series of Flash MCUs. Figure 50. 20-Pin QFN Package Diagram PS026407-0408 ZLF645 Series Flash MCUs Product Specification Packaging 171 ...
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Figure 51 displays the 28-pin shrink small outline package (SSOP) for the ZLF645 Series of Flash MCUs DETAIL SEATING PLANE Figure 51. 28-Pin SSOP Package Diagram PS026407-0408 ZLF645 Series ...
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Figure 52 displays the 28-pin small outline integrated circuit (SOIC) package for the ZLF645 Series of Flash MCUs. Figure 52. 28-Pin SOIC Package Diagram PS026407-0408 ZLF645 Series Flash MCUs Product Specification Packaging 173 ...
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Figure 53 displays the 28-pin plastic dual inline package (PDIP) for the ZLF645 Series of Flash MCUs. Z log Figure 53. 28-Pin PDIP Package Diagram PS026407-0408 ZLF645 Series Flash MCUs Product Specification Packaging 174 ...
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Figure 54 displays the 20-pin shrink small outline package (SSOP) for the ZLF645 Series of Flash MCUs. Figure 54. 20-Pin SSOP Package Diagram PS026407-0408 ZLF645 Series Flash MCUs Product Specification Packaging 175 ...
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Figure 55 displays the 20-pin small outline integrated circuit (SOIC) package for the ZLF645 Series of Flash MCUs. Figure 55. 20-Pin SOIC Package Diagram PS026407-0408 ZLF645 Series Flash MCUs Product Specification Packaging 176 ...
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Figure 56 displays the 20-pin plastic dual inline package (PDIP) for the ZLF645 Series of Flash MCUs. Figure 56. 20-Pin PDIP Package Diagram PS026407-0408 ZLF645 Series Flash MCUs Product Specification Packaging 177 ...
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Figure 57 displays the 48-pin shrink small outline package (SSOP) for the ZLF645 Series of Flash MCUs. Figure 57. 48-Pin SSOP Package Diagram PS026407-0408 ZLF645 Series Flash MCUs Product Specification 20984 178 05-07-07 M. Fonte Packaging ...
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Figure 58 displays the 20-pin Quad Flat No Lead (QFN) for the ZLF645 Series of Flash MCUs. PS026407-0408 Figure 58. 20-Pin QFN Package Diagram ZLF645 Series Flash MCUs Product Specification Packaging 179 ...
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... Table 88. ZLF645 Flash MCU Part Numbers Description Part Number ZLF645 Flash MCU with 512 B RAM ZLF645S0H2064G ZLF645S0H2864G ZLF645S0H4864G ZLF645S0P2064G ZLF645S0P2864G ZLF645S0S2064G ZLF645S0S2864G ZLF645S0Q2064G ZLF645S0H2032G ZLF645S0H2832G ZLF645S0H4832G ZLF645S0P2032G ZLF645S0P2832G ZLF645S0S2032G ZLF645S0S2832G ZLF645S0Q2032G ZLF645 Flash MCU with 1K RAM ZLF645E0H2064G ZLF645E0H2864G ZLF645E0H4864G ZLF645E0P2064G ZLF645E0P2864G ZLF645E0S2064G ZLF645E0S2864G PS026407-0408 ...
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Table 88. ZLF645 Flash MCU Part Numbers Description (Continued) Part Number ZLF645E0Q2064G ZLF645E0H2032G ZLF645E0H2832G ZLF645E0H4832G ZLF645E0P2032G ZLF645E0P2832G ZLF645E0S2032G ZLF645E0S2832G ZLF645E0Q2032G ZCRMZNICE01ZEMG ZCRMZN00100KITG ZCRMZNICE01ZACG ZCRMZNICE02ZACG PS026407-0408 ZLF645 Series Flash MCUs RAM Description Flash (KB QFN 20-pin package 32 1 ...
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... G = Lead Free (Green part) Flash Memory Number of Pins in Package 48 = 48-Pin 28 = 28-Pin 20 = 20-Pin Package Type H = SSOP P = PDIP S = SOIC Q = QFN RAM Size E0 = Extended 1K RAM S0 = Standard 512 B RAM Family Series Memory Type F = Flash Low Voltage Zilog Index ZLF645 Series Flash MCUs Product Specification Part Number Description 182 ...
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Index Numerics 11890 Figure Title Figure 34. Resets and WDT 12-bit address map 47 16-bit counter/timer circuits 103 20-pin package pins PDIP package 177, 178 SOIC package 176 SSOP package 175 28-pin package pins 11, 13, 16 ...
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CMOS gate, caution 18 comparator inputs 28 outputs 28 condition codes 156 conditions, test 159 connection, power 3 constant memory 41 constant, baud rate 91, 92 counter/timer block diagram 93 capture flowchart 100 input circuit ...
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ICP commands read ICP control register (05H) 59 read ICP revision (00H) 58 read ICP status ...
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OR caution 113 oscillator 129 output comparator 28 timer/counter 106 timer/counter circuit 107 timer/counter configuration 27 overline, in text 3 overrun, UART 85 P package diagram 171, 172, 173, 174, 175, 176, 177, 178 package information 171 parity, UART data ...
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SMR3 150 SMR4 151 SPL 48, 49 UCTL 90, 91 URDATA 89 USER 48 UST 89 UTDATA 89 WDTMR 137 register file 12-bit address 47 address summary 50 description 42 memory map 43 register pointer detail 44 example 45 Register ...
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T16 transmit 103 T16_OUT signal 104 T8 demodulation 99 T8 transmit 95 T8_OUT signal 98 transmit flowchart 96 transmit versus demodulation mode 115 Timer 16 Capture High Register (HI16) 109 Timer 16 Capture Low Register (L016) 110 Timer 16 Control ...
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... For answers to technical questions about the product, documentation, or any other issues with Zilog’s offerings, please visit Zilog’s Knowledge Base at http://www.zilog.com/kb. For any comments, detail technical questions, or reporting problems, please visit Zilog’s Technical Support at http://support.zilog.com. PS026407-0408 ZLF645 Series Flash MCUs ...