73S1210F-44M/F/PC Maxim Integrated Products, 73S1210F-44M/F/PC Datasheet - Page 75

• Manufacturer Part Number: 73S1210F-44M/F/PC
• Description: Microcontrollers (MCU)
• Manufacturer: Maxim Integrated Products

Specifications of 73S1210F-44M/F/PC

• Lead Free Status / Rohs Status: Details

DS_1210F_001
1.7.15.4
It is possible to bypass the smart card UART in order for the firmware to support non-T=0/T=1 smart
cards. This is called Bypass mode. In this mode the embedded firmware will communicate directly with
the selected smart card and drive I/O during transmit and read I/O during receive in order to communicate
with the smart card. In this mode, ATR processing is under firmware control. The firmware must
sequence the interface signals as required. Firmware must perform TS processing, parity checking,
break generation and CRC/LRC calculation (if required).
1.7.15.5
The 73S1210F supports synchronous operation. When sync mode is selected for either interface, the
CLK signal is generated by the ETU counter. The values in c, SCCLK, and
obtain the desired sync CLK rate. There is only one ETU counter and therefore, in sync mode, the
interface must be selected to obtain a smart card clock signal. In sync mode, input data is sampled on
the rise of CLK, and output data is changed on the fall of CLK.
Rev. 1.4
Bypass Mode
Synchronous Operation Mode
T = 1 Mode
ATR Timing Parameters
TRANSMISSION
BLOCK1
T = 0 Mode
IO
RLen(7:0)
RST
VCC_OK
CHAR 1
EGT
CHAR 1
Figure 19: Guard, Block, Wait and ATR Time Definitions
(By seting Last_TXByte and
TX/RXB=0 during CHAR N,
RX mode will start after last
TSTO(7:0)
CHAR 2
< WWT
> EGT
WWT is set by the value in the BWT registers.
TX byte)
CHAR N
IWT(15:0)
CHAR 1
> BWT
CHAR 2
ATRTO(15:0)
CHAR
CHAR 2
N+1
< CWT
RECEPTION
BLOCK2
CHAR
N+2
CHAR N
SCECLK
CHAR
N+3
BGT(4:0)
73S1210F Data Sheet
must be set to
TX
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