ADV7393BCPZ Analog Devices Inc, ADV7393BCPZ Datasheet - Page 93

• Manufacturer Part Number: ADV7393BCPZ
• Description: IC DAC VIDEO HDTV 10BIT 40LFCSP
• Manufacturer: Analog Devices Inc
• Type: Video Encoderr

Specifications of ADV7393BCPZ

• Design Resources: Reconstruction Video Filter Using ADA4430-1 Amplifier After ADV7393 Video Encoder (CN0101)
• Applications: Set-Top Boxes, Video Players, Displays
• Voltage - Supply, Analog: 2.6 V ~ 3.46 V
• Voltage - Supply, Digital: 1.71 V ~ 1.89 V
• Mounting Type: Surface Mount
• Package / Case: 40-LFCSP
• Input Format: Digital
• Output Format: Analog
• Supply Voltage Range: 1.71V To 1.89V
• Operating Temperature Range: -40°C To +85°C
• Tv / Video Case Style: LFCSP
• No. Of Pins: 40
• Msl: MSL 1 - Unlimited
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: ADV7393-DBRDZ - BOARD EVAL FOR ADV7393EVAL-ADV7393EBZ - BOARD EVAL FOR ADV7393 ENCODER
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Table 65. 8-Bit 525i YCrCb In (EAV/SAV), YPrPb Out
Subaddress
0x17
0x00
0x01
0x80
0x82
Table 66. 8-Bit 525i YCrCb In (EAV/SAV), CVBS/Y-C Out
Subaddress
0x17
0x00
0x01
0x80
0x82
Table 67. 8-Bit 525i YCrCb In, YPrPb Out
Subaddress
0x17
0x00
0x01
0x80
0x82
0x8A
Table 68. 8-Bit 525i YCrCb In (EAV/SAV), RGB Out
Subaddress
0x17
0x00
0x01
0x02
0x80
0x82
Setting
0x02
0x1C
0x00
0x10
0xC9
Setting
0x02
0x1C
0x10
0x00
0x10
0xCB
Setting
0x02
0x1C
0x00
0x10
0xC9
0x0C
Setting
0x02
0x1C
0x00
0x10
0x10
0xC9
Description
Software reset.
All DACs enabled. PLL enabled (16×).
SD input mode.
NTSC standard. SSAF luma filter
enabled.
1.3 MHz chroma filter enabled.
Pixel data valid. YPrPb out. SSAF PrPb
filter enabled. Active video edge
control enabled. Pedestal enabled.
Description
Software reset
All DACs enabled. PLL enabled (16×).
WLCSP required.
SD input mode.
NTSC standard. SSAF luma filter
enabled. 1.3 MHz chroma filter enabled.
Pixel data valid. CVBS/Y-C (S-Video)
out. SSAF PrPb filter enabled. Active
video edge control enabled. Pedestal
enabled.
Description
Software reset.
All DACs enabled. PLL enabled (16×).
SD input mode.
NTSC standard. SSAF luma filter
enabled. 1.3 MHz chroma filter enabled.
Pixel data valid. YPrPb out. SSAF PrPb
filter enabled. Active video edge
control enabled. Pedestal enabled.
Timing Mode 2 (slave). HSYNC/VSYNC
synchronization.
Description
Software reset.
All DACs enabled. PLL enabled (16×).
SD input mode.
RGB output enabled. RGB output sync
enabled.
NTSC standard. SSAF luma filter
enabled. 1.3 MHz chroma filter enabled.
Pixel data valid. RGB out. SSAF PrPb
filter enabled. Active video edge
control enabled. Pedestal enabled.
Rev. B | Page 93 of 108
Table 69. 8-Bit 525i YCrCb In, RGB Out
Subaddress
0x17
0x00
0x01
0x02
0x80
0x82
0x8A
Table 70. 10-Bit 525i YCrCb In (EAV/SAV), YPrPb Out
Subaddress
0x17
0x00
0x01
0x80
0x82
0x88
Table 71. 10-Bit 525i YCrCb In, YPrPb Out
Subaddress
0x17
0x00
0x01
0x80
0x82
0x88
0x8A
ADV7390/ADV7391/ADV7392/ADV7393
Setting
0x02
0x1C
0x00
0x10
0x10
0xC9
0x0C
Setting
0x02
0x1C
0x00
0x10
0xC9
0x10
Setting
0x02
0x1C
0x00
0x10
0xC9
0x10
0x0C
Description
Software reset.
All DACs enabled. PLL enabled (16×).
SD input mode.
RGB output enabled. RGB output sync
enabled.
NTSC standard. SSAF luma filter
enabled. 1.3 MHz chroma filter enabled.
Pixel data valid. RGB out. SSAF PrPb
filter enabled. Active video edge
control enabled. Pedestal enabled.
Timing Mode 2 (slave). HSYNC/VSYNC
synchronization.
Description
Software reset.
All DACs enabled. PLL enabled (16×).
SD input mode.
NTSC standard. SSAF luma filter
enabled. 1.3 MHz chroma filter enabled.
Pixel data valid. YPrPb out. SSAF PrPb
filter enabled. Active video edge
control enabled. Pedestal enabled.
10-bit input enabled.
Description
Software reset.
All DACs enabled. PLL enabled (16×).
SD input mode.
NTSC standard. SSAF luma filter
enabled. 1.3 MHz chroma filter enabled.
Pixel data valid. YPrPb out. SSAF PrPb
filter enabled. Active video edge
control enabled. Pedestal enabled.
10-bit input enabled.
Timing Mode 2 (slave). HSYNC/VSYNC
synchronization.